Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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2020-06-16 19:28:02 +01:00
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using System.Reflection;
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Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
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using static ARMeilleure.Instructions.InstEmitHelper;
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Reduce JIT GC allocations (#2515)
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
2021-08-17 19:08:34 +01:00
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Mcr(ArmEmitterContext context)
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{
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OpCode32System op = (OpCode32System)context.CurrOp;
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Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
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if (op.Coproc != 15 || op.Opc1 != 0)
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Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
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{
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2020-03-04 19:25:27 +00:00
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InstEmit.Und(context);
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2020-06-16 19:28:02 +01:00
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2020-03-04 19:25:27 +00:00
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return;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
MethodInfo info;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
switch (op.CRn)
|
|
|
|
|
{
|
|
|
|
|
case 13: // Process and Thread Info.
|
|
|
|
|
if (op.CRm != 0)
|
|
|
|
|
{
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
switch (op.Opc2)
|
|
|
|
|
{
|
|
|
|
|
case 2:
|
2020-06-16 19:28:02 +01:00
|
|
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032)); break;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 7:
|
|
|
|
|
switch (op.CRm) // Cache and Memory barrier.
|
|
|
|
|
{
|
|
|
|
|
case 10:
|
|
|
|
|
switch (op.Opc2)
|
|
|
|
|
{
|
|
|
|
|
case 5: // Data Memory Barrier Register.
|
|
|
|
|
return; // No-op.
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
default:
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
context.Call(info, GetIntA32(context, op.Rt));
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static void Mrc(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32System op = (OpCode32System)context.CurrOp;
|
|
|
|
|
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
if (op.Coproc != 15 || op.Opc1 != 0)
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
{
|
2020-03-04 19:25:27 +00:00
|
|
|
|
InstEmit.Und(context);
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
2020-03-04 19:25:27 +00:00
|
|
|
|
return;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
MethodInfo info;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
switch (op.CRn)
|
|
|
|
|
{
|
|
|
|
|
case 13: // Process and Thread Info.
|
|
|
|
|
if (op.CRm != 0)
|
|
|
|
|
{
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
switch (op.Opc2)
|
|
|
|
|
{
|
|
|
|
|
case 2:
|
2020-06-16 19:28:02 +01:00
|
|
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl032)); break;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
case 3:
|
2020-06-16 19:28:02 +01:00
|
|
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32)); break;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
break;
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (op.Rt == RegisterAlias.Aarch32Pc)
|
|
|
|
|
{
|
|
|
|
|
// Special behavior: copy NZCV flags into APSR.
|
2020-06-16 19:28:02 +01:00
|
|
|
|
EmitSetNzcv(context, context.Call(info));
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2020-06-16 19:28:02 +01:00
|
|
|
|
SetIntA32(context, op.Rt, context.Call(info));
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static void Mrrc(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32System op = (OpCode32System)context.CurrOp;
|
|
|
|
|
|
|
|
|
|
if (op.Coproc != 15)
|
|
|
|
|
{
|
2020-03-04 19:25:27 +00:00
|
|
|
|
InstEmit.Und(context);
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
2020-03-04 19:25:27 +00:00
|
|
|
|
return;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
int opc = op.MrrcOp;
|
|
|
|
|
|
|
|
|
|
MethodInfo info;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
|
|
|
|
|
switch (op.CRm)
|
|
|
|
|
{
|
|
|
|
|
case 14: // Timer.
|
|
|
|
|
switch (opc)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
2020-06-16 19:28:02 +01:00
|
|
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
break;
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
|
2020-06-16 19:28:02 +01:00
|
|
|
|
Operand result = context.Call(info);
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
|
|
|
|
|
SetIntA32(context, op.Rt, context.ConvertI64ToI32(result));
|
|
|
|
|
SetIntA32(context, op.CRn, context.ConvertI64ToI32(context.ShiftRightUI(result, Const(32))));
|
|
|
|
|
}
|
|
|
|
|
|
2022-08-05 18:03:50 +01:00
|
|
|
|
public static void Mrs(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32Mrs op = (OpCode32Mrs)context.CurrOp;
|
|
|
|
|
|
|
|
|
|
if (op.R)
|
|
|
|
|
{
|
|
|
|
|
throw new NotImplementedException("SPSR");
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2022-09-20 22:55:13 +01:00
|
|
|
|
Operand spsr = context.ShiftLeft(GetFlag(PState.VFlag), Const((int)PState.VFlag));
|
|
|
|
|
spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.CFlag), Const((int)PState.CFlag)));
|
|
|
|
|
spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.ZFlag), Const((int)PState.ZFlag)));
|
|
|
|
|
spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.NFlag), Const((int)PState.NFlag)));
|
|
|
|
|
spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.QFlag), Const((int)PState.QFlag)));
|
2022-08-05 18:03:50 +01:00
|
|
|
|
|
|
|
|
|
// TODO: Remaining flags.
|
|
|
|
|
|
|
|
|
|
SetIntA32(context, op.Rd, spsr);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-08-26 23:07:44 +01:00
|
|
|
|
public static void Msr(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32MsrReg op = (OpCode32MsrReg)context.CurrOp;
|
|
|
|
|
|
|
|
|
|
if (op.R)
|
|
|
|
|
{
|
|
|
|
|
throw new NotImplementedException("SPSR");
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if ((op.Mask & 8) != 0)
|
|
|
|
|
{
|
|
|
|
|
Operand value = GetIntA32(context, op.Rn);
|
|
|
|
|
|
|
|
|
|
EmitSetNzcv(context, value);
|
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
Operand q = context.BitwiseAnd(context.ShiftRightUI(value, Const((int)PState.QFlag)), Const(1));
|
2021-08-26 23:07:44 +01:00
|
|
|
|
|
|
|
|
|
SetFlag(context, PState.QFlag, q);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((op.Mask & 4) != 0)
|
|
|
|
|
{
|
|
|
|
|
throw new NotImplementedException("APSR_g");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((op.Mask & 2) != 0)
|
|
|
|
|
{
|
|
|
|
|
throw new NotImplementedException("CPSR_x");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((op.Mask & 1) != 0)
|
|
|
|
|
{
|
|
|
|
|
throw new NotImplementedException("CPSR_c");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
public static void Nop(ArmEmitterContext context) { }
|
|
|
|
|
|
|
|
|
|
public static void Vmrs(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
|
|
|
|
|
|
if (op.Rt == RegisterAlias.Aarch32Pc && op.Sreg == 0b0001)
|
|
|
|
|
{
|
|
|
|
|
// Special behavior: copy NZCV flags into APSR.
|
|
|
|
|
SetFlag(context, PState.VFlag, GetFpFlag(FPState.VFlag));
|
|
|
|
|
SetFlag(context, PState.CFlag, GetFpFlag(FPState.CFlag));
|
|
|
|
|
SetFlag(context, PState.ZFlag, GetFpFlag(FPState.ZFlag));
|
|
|
|
|
SetFlag(context, PState.NFlag, GetFpFlag(FPState.NFlag));
|
2020-06-16 19:28:02 +01:00
|
|
|
|
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (op.Sreg)
|
|
|
|
|
{
|
|
|
|
|
case 0b0000: // FPSID
|
|
|
|
|
throw new NotImplementedException("Supervisor Only");
|
|
|
|
|
case 0b0001: // FPSCR
|
2020-08-08 16:18:51 +01:00
|
|
|
|
EmitGetFpscr(context); return;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
case 0b0101: // MVFR2
|
|
|
|
|
throw new NotImplementedException("MVFR2");
|
|
|
|
|
case 0b0110: // MVFR1
|
|
|
|
|
throw new NotImplementedException("MVFR1");
|
|
|
|
|
case 0b0111: // MVFR0
|
|
|
|
|
throw new NotImplementedException("MVFR0");
|
|
|
|
|
case 0b1000: // FPEXC
|
|
|
|
|
throw new NotImplementedException("Supervisor Only");
|
2020-06-16 19:28:02 +01:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public static void Vmsr(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
|
|
|
|
|
|
switch (op.Sreg)
|
|
|
|
|
{
|
|
|
|
|
case 0b0000: // FPSID
|
|
|
|
|
throw new NotImplementedException("Supervisor Only");
|
|
|
|
|
case 0b0001: // FPSCR
|
2020-08-08 16:18:51 +01:00
|
|
|
|
EmitSetFpscr(context); return;
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
case 0b0101: // MVFR2
|
|
|
|
|
throw new NotImplementedException("MVFR2");
|
|
|
|
|
case 0b0110: // MVFR1
|
|
|
|
|
throw new NotImplementedException("MVFR1");
|
|
|
|
|
case 0b0111: // MVFR0
|
|
|
|
|
throw new NotImplementedException("MVFR0");
|
|
|
|
|
case 0b1000: // FPEXC
|
|
|
|
|
throw new NotImplementedException("Supervisor Only");
|
2020-06-16 19:28:02 +01:00
|
|
|
|
default:
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions
* PPTC version
* Fix VQADD/VQSUB
* Improve MRC/MCR handling and exception messages
In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
2022-09-10 01:47:38 +01:00
|
|
|
|
throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
private static void EmitSetNzcv(ArmEmitterContext context, Operand t)
|
|
|
|
|
{
|
2022-09-20 22:55:13 +01:00
|
|
|
|
Operand v = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.VFlag)), Const(1));
|
|
|
|
|
Operand c = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.CFlag)), Const(1));
|
|
|
|
|
Operand z = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.ZFlag)), Const(1));
|
|
|
|
|
Operand n = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.NFlag)), Const(1));
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
|
|
|
|
|
SetFlag(context, PState.VFlag, v);
|
|
|
|
|
SetFlag(context, PState.CFlag, c);
|
|
|
|
|
SetFlag(context, PState.ZFlag, z);
|
|
|
|
|
SetFlag(context, PState.NFlag, n);
|
|
|
|
|
}
|
2020-08-08 16:18:51 +01:00
|
|
|
|
|
|
|
|
|
private static void EmitGetFpscr(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
Operand fpscr = Const(0);
|
2020-08-08 16:18:51 +01:00
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
|
|
|
|
|
{
|
|
|
|
|
if (FPSCR.Mask.HasFlag((FPSCR)(1u << flag)))
|
|
|
|
|
{
|
|
|
|
|
fpscr = context.BitwiseOr(fpscr, context.ShiftLeft(GetFpFlag((FPState)flag), Const(flag)));
|
|
|
|
|
}
|
|
|
|
|
}
|
2020-08-08 16:18:51 +01:00
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
SetIntA32(context, op.Rt, fpscr);
|
2020-08-08 16:18:51 +01:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
private static void EmitSetFpscr(ArmEmitterContext context)
|
|
|
|
|
{
|
|
|
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
Operand fpscr = GetIntA32(context, op.Rt);
|
2020-08-08 16:18:51 +01:00
|
|
|
|
|
2022-09-20 22:55:13 +01:00
|
|
|
|
for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
|
|
|
|
|
{
|
|
|
|
|
if (FPSCR.Mask.HasFlag((FPSCR)(1u << flag)))
|
|
|
|
|
{
|
|
|
|
|
SetFpFlag(context, (FPState)flag, context.BitwiseAnd(context.ShiftRightUI(fpscr, Const(flag)), Const(1)));
|
|
|
|
|
}
|
|
|
|
|
}
|
2020-08-08 16:18:51 +01:00
|
|
|
|
}
|
Add most of the A32 instruction set to ARMeilleure (#897)
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure :weary:
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
2020-02-23 21:20:40 +00:00
|
|
|
|
}
|
|
|
|
|
}
|