2022-08-25 10:59:34 +01:00
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namespace ARMeilleure.Decoders
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{
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class OpCodeT32MemImm8D : OpCodeT32, IOpCode32Mem
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{
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public int Rt { get; }
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public int Rt2 { get; }
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public int Rn { get; }
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public bool WBack { get; }
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public bool IsLoad { get; }
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public bool Index { get; }
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public bool Add { get; }
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public int Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemImm8D(inst, address, opCode);
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public OpCodeT32MemImm8D(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Rt2 = (opCode >> 8) & 0xf;
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Rt = (opCode >> 12) & 0xf;
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Rn = (opCode >> 16) & 0xf;
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Index = ((opCode >> 24) & 1) != 0;
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Add = ((opCode >> 23) & 1) != 0;
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WBack = ((opCode >> 21) & 1) != 0;
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Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
* Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg)
* Bump PPTC version
2022-09-10 02:09:11 +01:00
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Immediate = (opCode & 0xff) << 2;
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2022-08-25 10:59:34 +01:00
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IsLoad = ((opCode >> 20) & 1) != 0;
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}
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}
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}
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