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T32: Implement B, B.cond, BL, BLX (#3155)
* Decoders: Make IsThumb a function of OpCode32 * OpCode32: Fix GetPc * T32: Implement B, B.cond, BL, BLX * rm usings
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8 changed files with 253 additions and 9 deletions
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@ -13,11 +13,25 @@ namespace ARMeilleure.Decoders
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Cond = (Condition)((uint)opCode >> 28);
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}
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public bool IsThumb()
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{
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return this is OpCodeT16 || this is OpCodeT32;
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}
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public uint GetPc()
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{
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// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
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// the PC actually points 2 instructions ahead.
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return (uint)Address + (uint)OpCodeSizeInBytes * 2;
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if (IsThumb())
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{
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// PC is ahead by 4 in thumb mode whether or not the current instruction
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// is 16 or 32 bit.
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return (uint)Address + 4u;
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}
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else
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{
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return (uint)Address + 8u;
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}
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}
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}
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}
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29
ARMeilleure/Decoders/OpCodeT32BImm20.cs
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29
ARMeilleure/Decoders/OpCodeT32BImm20.cs
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@ -0,0 +1,29 @@
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using ARMeilleure.Instructions;
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namespace ARMeilleure.Decoders
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{
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class OpCodeT32BImm20 : OpCodeT32, IOpCode32BImm
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{
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public long Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32BImm20(inst, address, opCode);
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public OpCodeT32BImm20(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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uint pc = GetPc();
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int imm11 = (opCode >> 0) & 0x7ff;
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int j2 = (opCode >> 11) & 1;
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int j1 = (opCode >> 13) & 1;
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int imm6 = (opCode >> 16) & 0x3f;
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int s = (opCode >> 26) & 1;
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int imm32 = imm11 | (imm6 << 11) | (j1 << 17) | (j2 << 18) | (s << 19);
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imm32 = (imm32 << 13) >> 12;
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Immediate = pc + imm32;
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Cond = (Condition)((opCode >> 22) & 0xf);
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}
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}
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}
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35
ARMeilleure/Decoders/OpCodeT32BImm24.cs
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35
ARMeilleure/Decoders/OpCodeT32BImm24.cs
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@ -0,0 +1,35 @@
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using ARMeilleure.Instructions;
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namespace ARMeilleure.Decoders
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{
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class OpCodeT32BImm24 : OpCodeT32, IOpCode32BImm
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{
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public long Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32BImm24(inst, address, opCode);
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public OpCodeT32BImm24(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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uint pc = GetPc();
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if (inst.Name == InstName.Blx)
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{
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pc &= ~3u;
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}
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int imm11 = (opCode >> 0) & 0x7ff;
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int j2 = (opCode >> 11) & 1;
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int j1 = (opCode >> 13) & 1;
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int imm10 = (opCode >> 16) & 0x3ff;
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int s = (opCode >> 26) & 1;
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int i1 = j1 ^ s ^ 1;
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int i2 = j2 ^ s ^ 1;
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int imm32 = imm11 | (imm10 << 11) | (i2 << 21) | (i1 << 22) | (s << 23);
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imm32 = (imm32 << 9) >> 8;
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Immediate = pc + imm32;
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}
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}
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}
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@ -1050,7 +1050,11 @@ namespace ARMeilleure.Decoders
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SetT32("11101011010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluRsImm.Create);
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SetT32("11101011000<xxxx0xxx<<<<xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluRsImm.Create);
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SetT32("11101010000<xxxx0xxx<<<<xxxxxxxx", InstName.And, InstEmit32.And, OpCodeT32AluRsImm.Create);
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SetT32("11110x<<<xxxxxxx10x0xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm20.Create);
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SetT32("11110xxxxxxxxxxx10x1xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm24.Create);
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SetT32("11101010001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT32AluRsImm.Create);
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SetT32("11110xxxxxxxxxxx11x1xxxxxxxxxxxx", InstName.Bl, InstEmit32.Bl, OpCodeT32BImm24.Create);
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SetT32("11110xxxxxxxxxxx11x0xxxxxxxxxxx0", InstName.Blx, InstEmit32.Blx, OpCodeT32BImm24.Create);
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SetT32("111010110001xxxx0xxx1111xxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT32AluRsImm.Create);
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SetT32("111010111011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluRsImm.Create);
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SetT32("11101010100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT32AluRsImm.Create);
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@ -128,7 +128,7 @@ namespace ARMeilleure.Instructions
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{
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Debug.Assert(value.Type == OperandType.I32);
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if (IsThumb(context.CurrOp))
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if (((OpCode32)context.CurrOp).IsThumb())
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{
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bool isReturn = IsA32Return(context);
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if (!isReturn)
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@ -34,7 +34,7 @@ namespace ARMeilleure.Instructions
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uint pc = op.GetPc();
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bool isThumb = IsThumb(context.CurrOp);
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bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
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uint currentPc = isThumb
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? pc | 1
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@ -61,7 +61,7 @@ namespace ARMeilleure.Instructions
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Operand addr = context.Copy(GetIntA32(context, op.Rm));
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Operand bitOne = context.BitwiseAnd(addr, Const(1));
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bool isThumb = IsThumb(context.CurrOp);
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bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
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uint currentPc = isThumb
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? (pc - 2) | 1
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@ -10,11 +10,6 @@ namespace ARMeilleure.Instructions
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{
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static class InstEmitHelper
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{
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public static bool IsThumb(OpCode op)
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{
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return op is OpCodeT16 || op is OpCodeT32;
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}
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public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)
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{
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Operand value = GetIntOrZR(context, rm);
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167
Ryujinx.Tests/Cpu/CpuTestT32Flow.cs
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167
Ryujinx.Tests/Cpu/CpuTestT32Flow.cs
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@ -0,0 +1,167 @@
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("T32Flow")]
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public sealed class CpuTestT32Flow : CpuTest32
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{
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[Test]
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public void TestT32B1()
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{
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// BNE label
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ThumbOpcode(0xf040);
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ThumbOpcode(0x8240);
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for (int i = 0; i < 576; i++)
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{
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ThumbOpcode(0xe7fe);
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}
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// label: BX LR
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ThumbOpcode(0x4770);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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public void TestT32B2()
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{
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// BNE label1
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ThumbOpcode(0xf040);
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ThumbOpcode(0x8242);
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// label2: BNE label3
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ThumbOpcode(0xf040);
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ThumbOpcode(0x8242);
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for (int i = 0; i < 576; i++)
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{
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ThumbOpcode(0xe7fe);
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}
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// label1: BNE label2
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ThumbOpcode(0xf47f);
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ThumbOpcode(0xadbc);
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// label3: BX LR
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ThumbOpcode(0x4770);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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public void TestT32B3()
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{
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// B.W label
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ThumbOpcode(0xf000);
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ThumbOpcode(0xba40);
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for (int i = 0; i < 576; i++)
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{
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ThumbOpcode(0xe7fe);
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}
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// label: BX LR
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ThumbOpcode(0x4770);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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public void TestT32B4()
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{
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// B.W label1
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ThumbOpcode(0xf000);
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ThumbOpcode(0xba42);
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// label2: B.W label3
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ThumbOpcode(0xf000);
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ThumbOpcode(0xba42);
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for (int i = 0; i < 576; i++)
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{
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ThumbOpcode(0xe7fe);
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}
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// label1: B.W label2
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ThumbOpcode(0xf7ff);
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ThumbOpcode(0xbdbc);
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// label3: BX LR
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ThumbOpcode(0x4770);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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public void TestT32Bl()
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{
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// BL label
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ThumbOpcode(0xf000);
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ThumbOpcode(0xf840);
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for (int i = 0; i < 64; i++)
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{
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ThumbOpcode(0xe7fe);
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}
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ThumbOpcode(0x4670); // label: MOV R0, LR
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ThumbOpcode(0x2100); // MOVS R1, #0
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ThumbOpcode(0x468e); // MOV LR, R1
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ThumbOpcode(0x4770); // BX LR
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(0x1005));
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}
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[Test]
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public void TestT32Blx1()
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{
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// BLX label
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ThumbOpcode(0xf000);
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ThumbOpcode(0xe840);
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for (int i = 0; i < 64; i++)
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{
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ThumbOpcode(0x4770);
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}
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// .arm ; label: MOV R0, LR
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Opcode(0xe1a0000e);
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// MOV LR, #0
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Opcode(0xe3a0e000);
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// BX LR
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Opcode(0xe12fff1e);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(0x1005));
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Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
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}
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[Test]
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public void TestT32Blx2()
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{
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// NOP
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ThumbOpcode(0xbf00);
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// BLX label
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ThumbOpcode(0xf000);
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ThumbOpcode(0xe840);
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for (int i = 0; i < 63; i++)
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{
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ThumbOpcode(0x4770);
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}
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// .arm ; label: MOV R0, LR
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Opcode(0xe1a0000e);
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// MOV LR, #0
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Opcode(0xe3a0e000);
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// BX LR
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Opcode(0xe12fff1e);
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GetContext().SetPstateFlag(PState.TFlag, true);
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(0x1007));
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Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
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}
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}
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}
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