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Ryujinx/Ryujinx.Tests/Cpu
gdkchan 0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
* Refactor CPU interface

* Use IExecutionContext interface on SVC handler, change how CPU interrupts invokes the handlers

* Make CpuEngine take a ITickSource rather than returning one

The previous implementation had the scenario where the CPU engine had to implement the tick source in mind, like for example, when we have a hypervisor and the game can read CNTPCT on the host directly. However given that we need to do conversion due to different frequencies anyway, it's not worth it. It's better to just let the user pass the tick source and redirect any reads to CNTPCT to the user tick source

* XML docs for the public interfaces

* PPTC invalidation due to NativeInterface function name changes

* Fix build of the CPU tests

* PR feedback
2022-05-31 16:29:35 -03:00
..
CpuContext.cs Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 2022-05-31 16:29:35 -03:00
CpuTest.cs Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 2022-05-31 16:29:35 -03:00
CpuTest32.cs Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 2022-05-31 16:29:35 -03:00
CpuTestAlu.cs
CpuTestAlu32.cs ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089) 2022-02-08 10:46:42 +01:00
CpuTestAluBinary.cs
CpuTestAluBinary32.cs
CpuTestAluImm.cs
CpuTestAluImm32.cs A32: Fix ALU immediate instructions (#3179) 2022-03-05 15:23:10 -03:00
CpuTestAluRs.cs
CpuTestAluRs32.cs
CpuTestAluRx.cs
CpuTestBf32.cs
CpuTestBfm.cs
CpuTestCcmpImm.cs
CpuTestCcmpReg.cs Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) 2018-11-01 01:22:09 -03:00
CpuTestCsel.cs
CpuTestMisc.cs
CpuTestMisc32.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
CpuTestMov.cs Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696) 2019-06-12 09:03:31 -03:00
CpuTestMul.cs
CpuTestMul32.cs
CpuTestSimd.cs CPU - Implement FCVTMS (Vector) (#2937) 2022-01-04 16:45:28 -03:00
CpuTestSimd32.cs Implement VCNT instruction (#1963) 2021-02-22 16:26:13 +01:00
CpuTestSimdCrypto.cs
CpuTestSimdCrypto32.cs
CpuTestSimdCvt.cs Implement FCVTNS (Scalar GP) (#2953) 2022-01-19 22:21:44 -03:00
CpuTestSimdCvt32.cs Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775) 2020-12-17 20:43:41 +01:00
CpuTestSimdExt.cs
CpuTestSimdFcond.cs
CpuTestSimdFmov.cs
CpuTestSimdImm.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
CpuTestSimdIns.cs
CpuTestSimdLogical32.cs Implement VORN (register) Arm32 instruction (#2396) 2021-06-23 23:21:23 +02:00
CpuTestSimdMemory32.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
CpuTestSimdMov32.cs
CpuTestSimdReg.cs CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) 2021-01-04 23:45:54 +01:00
CpuTestSimdReg32.cs CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) 2021-01-04 23:45:54 +01:00
CpuTestSimdRegElem.cs Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) 2021-03-25 23:33:32 +01:00
CpuTestSimdRegElem32.cs
CpuTestSimdRegElemF.cs
CpuTestSimdShImm.cs CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) 2020-08-31 20:48:21 -03:00
CpuTestSimdShImm32.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
CpuTestSimdTbl.cs Add Tbx Inst. (fast & slow paths), with Tests. (#782) 2019-10-04 11:43:20 -03:00
CpuTestSystem.cs
CpuTestT32Alu.cs T32: Implement Data Processing (Modified Immediate) instructions (#3178) 2022-03-06 22:25:01 +01:00
CpuTestT32Flow.cs T32: Implement B, B.cond, BL, BLX (#3155) 2022-03-04 23:05:08 +01:00
CpuTestT32Mem.cs T32: Implement load/store single (immediate) (#3186) 2022-04-21 01:25:43 +02:00
CpuTestThumb.cs T32: Implement ALU (shifted register) instructions (#3135) 2022-02-22 19:11:28 -03:00
PrecomputedMemoryThumbTestCase.cs T32: Implement load/store single (immediate) (#3186) 2022-04-21 01:25:43 +02:00
PrecomputedThumbTestCase.cs T32: Implement ALU (shifted register) instructions (#3135) 2022-02-22 19:11:28 -03:00