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f0824fde9f
* Add host CPU memory barriers for DMB/DSB and ordered load/store * PPTC version bump * Revert to old barrier order
72 lines
No EOL
1.4 KiB
C#
72 lines
No EOL
1.4 KiB
C#
namespace ARMeilleure.IntermediateRepresentation
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{
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enum Instruction : ushort
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{
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Add,
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BitwiseAnd,
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BitwiseExclusiveOr,
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BitwiseNot,
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BitwiseOr,
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BranchIf,
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ByteSwap,
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Call,
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Compare,
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CompareAndSwap,
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CompareAndSwap16,
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CompareAndSwap8,
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ConditionalSelect,
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ConvertI64ToI32,
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ConvertToFP,
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ConvertToFPUI,
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Copy,
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CountLeadingZeros,
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Divide,
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DivideUI,
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Load,
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Load16,
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Load8,
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LoadArgument,
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MemoryBarrier,
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Multiply,
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Multiply64HighSI,
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Multiply64HighUI,
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Negate,
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Return,
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RotateRight,
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ShiftLeft,
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ShiftRightSI,
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ShiftRightUI,
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SignExtend16,
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SignExtend32,
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SignExtend8,
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StackAlloc,
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Store,
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Store16,
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Store8,
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Subtract,
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Tailcall,
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VectorCreateScalar,
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VectorExtract,
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VectorExtract16,
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VectorExtract8,
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VectorInsert,
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VectorInsert16,
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VectorInsert8,
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VectorOne,
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VectorZero,
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VectorZeroUpper64,
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VectorZeroUpper96,
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ZeroExtend16,
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ZeroExtend32,
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ZeroExtend8,
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Clobber,
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Extended,
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Fill,
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LoadFromContext,
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Phi,
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Spill,
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SpillArg,
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StoreToContext
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}
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} |