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10c74182ba
* Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
61 lines
1.5 KiB
C#
61 lines
1.5 KiB
C#
#define SimdFmov
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdFmov")]
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public sealed class CpuTestSimdFmov : CpuTest
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{
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#if SimdFmov
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#region "ValueSource"
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private static uint[] _F_Mov_Si_S_()
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{
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return new uint[]
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{
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0x1E201000u // FMOV S0, #2.0
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};
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}
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private static uint[] _F_Mov_Si_D_()
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{
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return new uint[]
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{
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0x1E601000u // FMOV D0, #2.0
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};
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}
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#endregion
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[Test, Pairwise] [Explicit]
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public void F_Mov_Si_S([ValueSource("_F_Mov_Si_S_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint imm8)
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{
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opcodes |= ((imm8 & 0xFFu) << 13);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Si_D([ValueSource("_F_Mov_Si_D_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint imm8)
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{
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opcodes |= ((imm8 & 0xFFu) << 13);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE1(z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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