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https://github.com/Ryujinx/Ryujinx.git
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295fbd0542
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection
Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.
* ARMeilleure: Add initial support for EVEX instruction encoding
Does not implement rounding, or exception controls.
* ARMeilleure: Add `X86Vpternlogd`
Accelerates the vector-`Not` instruction.
* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}
* ARMeilleure: Add check for `XCR0` flags
Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.
* ARMeilleure: Increment InternalVersion
* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting
* ARMeilleure: Move XCR0 procedure to GetXcr0Eax
* ARMeilleure: Add `XCR0` to `FeatureInfo` structure
* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly
Avoids an additional allocation
* ARMeilleure: Formatting fixes
178 lines
No EOL
3.4 KiB
C#
178 lines
No EOL
3.4 KiB
C#
namespace ARMeilleure.IntermediateRepresentation
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{
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enum Intrinsic : ushort
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{
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X86Addpd,
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X86Addps,
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X86Addsd,
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X86Addss,
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X86Aesdec,
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X86Aesdeclast,
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X86Aesenc,
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X86Aesenclast,
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X86Aesimc,
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X86Andnpd,
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X86Andnps,
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X86Andpd,
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X86Andps,
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X86Blendvpd,
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X86Blendvps,
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X86Cmppd,
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X86Cmpps,
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X86Cmpsd,
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X86Cmpss,
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X86Comisdeq,
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X86Comisdge,
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X86Comisdlt,
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X86Comisseq,
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X86Comissge,
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X86Comisslt,
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X86Crc32,
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X86Crc32_16,
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X86Crc32_8,
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X86Cvtdq2pd,
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X86Cvtdq2ps,
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X86Cvtpd2dq,
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X86Cvtpd2ps,
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X86Cvtps2dq,
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X86Cvtps2pd,
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X86Cvtsd2si,
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X86Cvtsd2ss,
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X86Cvtsi2sd,
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X86Cvtsi2si,
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X86Cvtsi2ss,
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X86Cvtss2sd,
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X86Cvtss2si,
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X86Divpd,
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X86Divps,
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X86Divsd,
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X86Divss,
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X86Gf2p8affineqb,
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X86Haddpd,
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X86Haddps,
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X86Insertps,
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X86Maxpd,
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X86Maxps,
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X86Maxsd,
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X86Maxss,
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X86Minpd,
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X86Minps,
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X86Minsd,
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X86Minss,
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X86Movhlps,
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X86Movlhps,
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X86Movss,
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X86Mulpd,
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X86Mulps,
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X86Mulsd,
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X86Mulss,
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X86Mxcsrmb,
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X86Mxcsrub,
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X86Paddb,
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X86Paddd,
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X86Paddq,
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X86Paddw,
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X86Palignr,
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X86Pand,
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X86Pandn,
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X86Pavgb,
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X86Pavgw,
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X86Pblendvb,
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X86Pclmulqdq,
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X86Pcmpeqb,
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X86Pcmpeqd,
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X86Pcmpeqq,
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X86Pcmpeqw,
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X86Pcmpgtb,
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X86Pcmpgtd,
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X86Pcmpgtq,
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X86Pcmpgtw,
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X86Pmaxsb,
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X86Pmaxsd,
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X86Pmaxsw,
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X86Pmaxub,
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X86Pmaxud,
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X86Pmaxuw,
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X86Pminsb,
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X86Pminsd,
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X86Pminsw,
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X86Pminub,
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X86Pminud,
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X86Pminuw,
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X86Pmovsxbw,
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X86Pmovsxdq,
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X86Pmovsxwd,
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X86Pmovzxbw,
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X86Pmovzxdq,
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X86Pmovzxwd,
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X86Pmulld,
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X86Pmullw,
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X86Popcnt,
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X86Por,
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X86Pshufb,
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X86Pshufd,
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X86Pslld,
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X86Pslldq,
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X86Psllq,
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X86Psllw,
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X86Psrad,
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X86Psraw,
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X86Psrld,
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X86Psrlq,
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X86Psrldq,
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X86Psrlw,
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X86Psubb,
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X86Psubd,
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X86Psubq,
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X86Psubw,
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X86Punpckhbw,
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X86Punpckhdq,
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X86Punpckhqdq,
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X86Punpckhwd,
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X86Punpcklbw,
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X86Punpckldq,
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X86Punpcklqdq,
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X86Punpcklwd,
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X86Pxor,
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X86Rcpps,
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X86Rcpss,
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X86Roundpd,
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X86Roundps,
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X86Roundsd,
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X86Roundss,
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X86Rsqrtps,
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X86Rsqrtss,
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X86Sha256Msg1,
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X86Sha256Msg2,
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X86Sha256Rnds2,
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X86Shufpd,
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X86Shufps,
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X86Sqrtpd,
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X86Sqrtps,
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X86Sqrtsd,
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X86Sqrtss,
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X86Subpd,
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X86Subps,
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X86Subsd,
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X86Subss,
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X86Unpckhpd,
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X86Unpckhps,
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X86Unpcklpd,
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X86Unpcklps,
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X86Vcvtph2ps,
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X86Vcvtps2ph,
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X86Vfmadd231ps,
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X86Vfmadd231sd,
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X86Vfmadd231ss,
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X86Vfmsub231sd,
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X86Vfmsub231ss,
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X86Vfnmadd231ps,
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X86Vfnmadd231sd,
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X86Vfnmadd231ss,
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X86Vfnmsub231sd,
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X86Vfnmsub231ss,
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X86Vpternlogd,
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X86Xorpd,
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X86Xorps
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}
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} |