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326777ca4a
* Ryujinx.Tests: Add unicorn to test framework * CpuTestSimdArithmetic: Comment out inaccurate results
296 lines
3.8 KiB
C#
296 lines
3.8 KiB
C#
using System;
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namespace Ryujinx.Tests.Unicorn.Native
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{
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public enum ArmRegister
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{
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INVALID = 0,
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X29,
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X30,
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NZCV,
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SP,
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WSP,
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WZR,
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XZR,
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B0,
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B1,
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B2,
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B3,
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B4,
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B5,
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B6,
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B7,
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B8,
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B9,
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B10,
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B11,
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B12,
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B13,
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B14,
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B15,
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B16,
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B17,
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B18,
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B19,
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B20,
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B21,
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B22,
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B23,
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B24,
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B25,
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B26,
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B27,
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B28,
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B29,
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B30,
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B31,
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D0,
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D1,
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D2,
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D3,
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D4,
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D5,
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D6,
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D7,
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D8,
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D9,
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D10,
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D11,
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D12,
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D13,
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D14,
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D15,
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D16,
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D17,
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D18,
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D19,
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D20,
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D21,
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D22,
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D23,
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D24,
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D25,
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D26,
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D27,
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D28,
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D29,
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D30,
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D31,
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H0,
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H1,
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H2,
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H3,
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H4,
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H5,
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H6,
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H7,
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H8,
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H9,
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H10,
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H11,
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H12,
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H13,
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H14,
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H15,
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H16,
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H17,
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H18,
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H19,
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H20,
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H21,
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H22,
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H23,
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H24,
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H25,
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H26,
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H27,
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H28,
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H29,
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H30,
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H31,
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Q0,
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Q1,
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Q2,
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Q3,
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Q4,
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Q5,
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Q6,
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Q7,
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Q8,
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Q9,
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Q10,
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Q11,
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Q12,
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Q13,
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Q14,
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Q15,
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Q16,
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Q17,
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Q18,
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Q19,
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Q20,
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Q21,
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Q22,
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Q23,
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Q24,
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Q25,
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Q26,
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Q27,
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Q28,
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Q29,
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Q30,
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Q31,
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S0,
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S1,
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S2,
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S3,
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S4,
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S5,
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S6,
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S7,
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S8,
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S9,
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S10,
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S11,
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S12,
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S13,
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S14,
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S15,
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S16,
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S17,
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S18,
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S19,
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S20,
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S21,
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S22,
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S23,
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S24,
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S25,
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S26,
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S27,
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S28,
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S29,
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S30,
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S31,
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W0,
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W1,
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W2,
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W3,
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W4,
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W5,
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W6,
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W7,
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W8,
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W9,
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W10,
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W11,
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W12,
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W13,
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W14,
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W15,
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W16,
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W17,
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W18,
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W19,
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W20,
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W21,
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W22,
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W23,
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W24,
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W25,
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W26,
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W27,
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W28,
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W29,
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W30,
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X0,
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X1,
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X2,
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X3,
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X4,
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X5,
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X6,
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X7,
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X8,
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X9,
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X10,
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X11,
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X12,
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X13,
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X14,
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X15,
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X16,
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X17,
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X18,
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X19,
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X20,
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X21,
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X22,
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X23,
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X24,
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X25,
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X26,
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X27,
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X28,
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V0,
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V1,
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V2,
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V3,
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V4,
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V5,
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V6,
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V7,
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V8,
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V9,
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V10,
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V11,
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V12,
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V13,
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V14,
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V15,
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V16,
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V17,
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V18,
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V19,
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V20,
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V21,
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V22,
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V23,
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V24,
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V25,
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V26,
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V27,
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V28,
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V29,
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V30,
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V31,
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//> pseudo registers
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PC, // program counter register
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CPACR_EL1,
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ESR,
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//> thread registers
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TPIDR_EL0,
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TPIDRRO_EL0,
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TPIDR_EL1,
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PSTATE, // PSTATE pseudoregister
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//> floating point control and status registers
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FPCR,
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FPSR,
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ENDING, // <-- mark the end of the list of registers
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//> alias registers
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IP0 = X16,
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IP1 = X17,
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FP = X29,
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LR = X30,
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}
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}
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