LDj3SNuD 2ccd995cb2 Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92) ... * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Create CpuTestSimd.cs * Create CpuTestSimdReg.cs * Update CpuTestSimd.cs Provide a better supply of input values for the 20 Simd Tests. * Update CpuTestSimdReg.cs Provide a better supply of input values for the 20 Simd Tests. * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs		2018-04-20 12:40:15 -03:00
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AInst.cs
AInstEmitAlu.cs	Add Cls Instruction. (#67)	2018-03-23 22:06:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs	Allow more than one process, free resources on process dispose, implement SvcExitThread	2018-03-12 01:14:12 -03:00
AInstEmitFlow.cs	Improve CPU initial translation speeds (#50)	2018-03-04 14:09:59 -03:00
AInstEmitHash.cs	Remove unused function from CPU	2018-03-14 00:57:07 -03:00
AInstEmitMemory.cs
AInstEmitMemoryEx.cs
AInstEmitMemoryHelper.cs	Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks	2018-03-10 20:39:16 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs	Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92)	2018-04-20 12:40:15 -03:00
AInstEmitSimdCmp.cs	Fix FRSQRTS and FCM* (scalar) instructions	2018-04-06 10:20:17 -03:00
AInstEmitSimdCvt.cs	Add MUL (vector by element), fix FCVTN, make svcs use MakeError too	2018-03-05 16:18:37 -03:00
AInstEmitSimdHelper.cs	Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)	2018-04-08 16:08:57 -03:00
AInstEmitSimdLogical.cs	Add BIT instruction	2018-03-30 16:46:00 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs	Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)	2018-04-12 11:52:00 -03:00
AInstEmitSimdShift.cs	CPU fix for the cases using a Mask with shift = 0	2018-03-14 01:59:22 -03:00
AInstEmitSystem.cs	Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count	2018-03-13 21:24:32 -03:00
AInstEmitter.cs
ASoftFallback.cs	Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)	2018-04-19 00:22:12 -03:00
ASoftFloat.cs	Implement Frsqrte_S (#72)	2018-04-05 20:36:19 -03:00