mirror of
https://github.com/Ryujinx/Ryujinx.git
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9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
185 lines
No EOL
5.1 KiB
C#
185 lines
No EOL
5.1 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmitMemoryHelper;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Ld__Vms(ILEmitterCtx context)
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{
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EmitSimdMemMs(context, isLoad: true);
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}
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public static void Ld__Vss(ILEmitterCtx context)
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{
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EmitSimdMemSs(context, isLoad: true);
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}
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public static void St__Vms(ILEmitterCtx context)
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{
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EmitSimdMemMs(context, isLoad: false);
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}
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public static void St__Vss(ILEmitterCtx context)
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{
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EmitSimdMemSs(context, isLoad: false);
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}
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private static void EmitSimdMemMs(ILEmitterCtx context, bool isLoad)
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{
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OpCodeSimdMemMs64 op = (OpCodeSimdMemMs64)context.CurrOp;
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int offset = 0;
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for (int rep = 0; rep < op.Reps; rep++)
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for (int elem = 0; elem < op.Elems; elem++)
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rtt = (op.Rt + rep + sElem) & 0x1f;
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if (isLoad)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(op.Rn);
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context.EmitLdc_I8(offset);
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context.Emit(OpCodes.Add);
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EmitReadZxCall(context, op.Size);
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EmitVectorInsert(context, rtt, elem, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1)
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{
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EmitVectorZeroUpper(context, rtt);
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}
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}
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else
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(op.Rn);
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context.EmitLdc_I8(offset);
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context.Emit(OpCodes.Add);
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EmitVectorExtractZx(context, rtt, elem, op.Size);
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EmitWriteCall(context, op.Size);
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}
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offset += 1 << op.Size;
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemSs(ILEmitterCtx context, bool isLoad)
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{
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OpCodeSimdMemSs64 op = (OpCodeSimdMemSs64)context.CurrOp;
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int offset = 0;
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void EmitMemAddress()
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(op.Rn);
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context.EmitLdc_I8(offset);
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context.Emit(OpCodes.Add);
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}
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if (op.Replicate)
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{
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//Only loads uses the replicate mode.
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if (!isLoad)
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{
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throw new InvalidOperationException();
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}
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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for (int index = 0; index < elems; index++)
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{
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EmitMemAddress();
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EmitReadZxCall(context, op.Size);
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EmitVectorInsert(context, rt, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, rt);
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}
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offset += 1 << op.Size;
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}
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}
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else
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{
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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if (isLoad)
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{
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EmitMemAddress();
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EmitReadZxCall(context, op.Size);
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EmitVectorInsert(context, rt, op.Index, op.Size);
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}
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else
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{
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EmitMemAddress();
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EmitVectorExtractZx(context, rt, op.Index, op.Size);
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EmitWriteCall(context, op.Size);
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}
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offset += 1 << op.Size;
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}
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemWBack(ILEmitterCtx context, int offset)
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{
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OpCodeMemReg64 op = (OpCodeMemReg64)context.CurrOp;
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context.EmitLdint(op.Rn);
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if (op.Rm != CpuThreadState.ZrIndex)
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{
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context.EmitLdint(op.Rm);
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}
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else
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{
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context.EmitLdc_I8(offset);
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}
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context.Emit(OpCodes.Add);
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context.EmitStint(op.Rn);
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}
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}
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} |