merry 7b35ebc64a T32: Implement ALU (shifted register) instructions (#3135) ... * T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2		2022-02-22 19:11:28 -03:00
..
CpuTest.cs	Add multi-level function table (#2228)	2021-05-29 18:06:28 -03:00
CpuTest32.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
CpuTestAlu.cs
CpuTestAlu32.cs	ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)	2022-02-08 10:46:42 +01:00
CpuTestAluBinary.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
CpuTestAluBinary32.cs
CpuTestAluImm.cs
CpuTestAluRs.cs
CpuTestAluRs32.cs
CpuTestAluRx.cs
CpuTestBf32.cs
CpuTestBfm.cs
CpuTestCcmpImm.cs
CpuTestCcmpReg.cs
CpuTestCsel.cs
CpuTestMisc.cs
CpuTestMisc32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestMov.cs
CpuTestMul.cs
CpuTestMul32.cs
CpuTestSimd.cs	CPU - Implement FCVTMS (Vector) (#2937)	2022-01-04 16:45:28 -03:00
CpuTestSimd32.cs	Implement VCNT instruction (#1963)	2021-02-22 16:26:13 +01:00
CpuTestSimdCrypto.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdCrypto32.cs
CpuTestSimdCvt.cs	Implement FCVTNS (Scalar GP) (#2953)	2022-01-19 22:21:44 -03:00
CpuTestSimdCvt32.cs	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
CpuTestSimdExt.cs
CpuTestSimdFcond.cs
CpuTestSimdFmov.cs
CpuTestSimdImm.cs
CpuTestSimdIns.cs
CpuTestSimdLogical32.cs	Implement VORN (register) Arm32 instruction (#2396)	2021-06-23 23:21:23 +02:00
CpuTestSimdMemory32.cs
CpuTestSimdMov32.cs
CpuTestSimdReg.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
CpuTestSimdReg32.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
CpuTestSimdRegElem.cs	Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)	2021-03-25 23:33:32 +01:00
CpuTestSimdRegElem32.cs
CpuTestSimdRegElemF.cs
CpuTestSimdShImm.cs
CpuTestSimdShImm32.cs
CpuTestSimdTbl.cs
CpuTestSystem.cs
CpuTestT32Alu.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
CpuTestThumb.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
PrecomputedThumbTestCase.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00