mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-15 07:36:39 +00:00
814f75142e
* Implemented in IR the managed methods of the Saturating region ... ... of the SoftFallback class (the SatQ ones). The need to natively manage the Fpcr and Fpsr system registers is still a fact. Contributes to https://github.com/Ryujinx/Ryujinx/issues/2917 ; I will open another PR to implement in Intrinsics-branchless the methods of the Saturation region as well (the SatXXXToXXX ones). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Ptc.InternalVersion = 3665 * Addressed PR feedback. * Implemented in IR the managed methods of the ShlReg region of the SoftFallback class. It also includes the last two SatQ ones (following up on https://github.com/Ryujinx/Ryujinx/pull/3665). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Fpsr and Fpcr freed. Handling/isolation of Fpsr and Fpcr via register for IR and via memory for Tests and Threads, with synchronization to context exchanges (explicit for SoftFloat); without having to call managed methods. Thanks to the inlining work of the previous two PRs and others in this. Tests performed locally in both release and debug modes, in both lowcq and highcq, with FastFP to true and false (explicit FP tests included). Tested with the title Tony Hawk's PS. Depends on shlreg. * Update InstEmitSimdHelper.cs * De-magic Masks. Remove the Stride and Len flags; Fpsr.NZCV are A32 only, then moved to Fpscr: this leads to emitting less IR in reference to Get/Set Fpsr/Fpcr/Fpscr methods in reference to Mrs/Msr (A64) and Vmrs/Vmsr (A32) instructions. * Addressed PR feedback.
389 lines
14 KiB
C#
389 lines
14 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Vqrshrn(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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EmitRoundShrImmSaturatingNarrowOp(context, op.U ? ShrImmSaturatingNarrowFlags.VectorZxZx : ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Vqrshrun(ArmEmitterContext context)
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{
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EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Vqshrn(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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EmitShrImmSaturatingNarrowOp(context, op.U ? ShrImmSaturatingNarrowFlags.VectorZxZx : ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Vqshrun(ArmEmitterContext context)
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{
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EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Vrshr(ArmEmitterContext context)
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{
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EmitRoundShrImmOp(context, accumulate: false);
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}
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public static void Vrshrn(ArmEmitterContext context)
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{
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EmitRoundShrImmNarrowOp(context, signed: false);
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}
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public static void Vrsra(ArmEmitterContext context)
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{
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EmitRoundShrImmOp(context, accumulate: true);
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}
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public static void Vshl(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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EmitVectorUnaryOpZx32(context, (op1) => context.ShiftLeft(op1, Const(op.Shift)));
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}
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public static void Vshl_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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if (op.U)
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => EmitShlRegOp(context, op2, op1, op.Size, true));
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}
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else
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{
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EmitVectorBinaryOpSx32(context, (op1, op2) => EmitShlRegOp(context, op2, op1, op.Size, false));
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}
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}
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public static void Vshll(ArmEmitterContext context)
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{
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OpCode32SimdShImmLong op = (OpCode32SimdShImmLong)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
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if (op.Size == 2)
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{
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if (op.U)
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{
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me = context.ZeroExtend32(OperandType.I64, me);
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}
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else
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{
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me = context.SignExtend32(OperandType.I64, me);
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}
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}
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me = context.ShiftLeft(me, Const(op.Shift));
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res = EmitVectorInsert(context, res, me, index, op.Size + 1);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vshr(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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int maxShift = (8 << op.Size) - 1;
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if (op.U)
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{
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EmitVectorUnaryOpZx32(context, (op1) => (shift > maxShift) ? Const(op1.Type, 0) : context.ShiftRightUI(op1, Const(shift)));
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}
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else
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{
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EmitVectorUnaryOpSx32(context, (op1) => context.ShiftRightSI(op1, Const(Math.Min(maxShift, shift))));
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}
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}
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public static void Vshrn(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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EmitVectorUnaryNarrowOp32(context, (op1) => context.ShiftRightUI(op1, Const(shift)));
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}
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public static void Vsra(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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int maxShift = (8 << op.Size) - 1;
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if (op.U)
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{
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EmitVectorImmBinaryQdQmOpZx32(context, (op1, op2) =>
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{
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Operand shiftRes = shift > maxShift ? Const(op2.Type, 0) : context.ShiftRightUI(op2, Const(shift));
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return context.Add(op1, shiftRes);
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});
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}
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else
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{
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EmitVectorImmBinaryQdQmOpSx32(context, (op1, op2) => context.Add(op1, context.ShiftRightSI(op2, Const(Math.Min(maxShift, shift)))));
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}
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}
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public static void EmitRoundShrImmOp(ArmEmitterContext context, bool accumulate)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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long roundConst = 1L << (shift - 1);
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if (op.U)
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{
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if (op.Size < 2)
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{
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EmitVectorUnaryOpZx32(context, (op1) =>
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{
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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return context.ShiftRightUI(op1, Const(shift));
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}, accumulate);
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}
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else if (op.Size == 2)
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{
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EmitVectorUnaryOpZx32(context, (op1) =>
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{
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op1 = context.ZeroExtend32(OperandType.I64, op1);
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
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}, accumulate);
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}
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else /* if (op.Size == 3) */
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{
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EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift), accumulate);
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}
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}
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else
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{
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if (op.Size < 2)
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{
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EmitVectorUnaryOpSx32(context, (op1) =>
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{
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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return context.ShiftRightSI(op1, Const(shift));
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}, accumulate);
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}
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else if (op.Size == 2)
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{
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EmitVectorUnaryOpSx32(context, (op1) =>
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{
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op1 = context.SignExtend32(OperandType.I64, op1);
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
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}, accumulate);
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}
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else /* if (op.Size == 3) */
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{
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EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift), accumulate);
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}
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}
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}
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private static void EmitRoundShrImmNarrowOp(ArmEmitterContext context, bool signed)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = GetImmShr(op);
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long roundConst = 1L << (shift - 1);
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EmitVectorUnaryNarrowOp32(context, (op1) =>
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{
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if (op.Size <= 1)
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{
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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op1 = signed ? context.ShiftRightSI(op1, Const(shift)) : context.ShiftRightUI(op1, Const(shift));
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}
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else /* if (op.Size == 2 && round) */
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{
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op1 = EmitShrImm64(context, op1, signed, roundConst, shift); // shift <= 32
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}
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return op1;
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}, signed);
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}
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private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned)
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{
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if (shiftLsB.Type == OperandType.I64)
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{
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shiftLsB = context.ConvertI64ToI32(shiftLsB);
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}
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shiftLsB = context.SignExtend8(OperandType.I32, shiftLsB);
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Debug.Assert((uint)size < 4u);
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Operand negShiftLsB = context.Negate(shiftLsB);
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Operand isPositive = context.ICompareGreaterOrEqual(shiftLsB, Const(0));
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Operand shl = context.ShiftLeft(op, shiftLsB);
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Operand shr = unsigned ? context.ShiftRightUI(op, negShiftLsB) : context.ShiftRightSI(op, negShiftLsB);
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Operand res = context.ConditionalSelect(isPositive, shl, shr);
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if (unsigned)
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{
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Operand isOutOfRange = context.BitwiseOr(
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context.ICompareGreaterOrEqual(shiftLsB, Const(8 << size)),
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context.ICompareGreaterOrEqual(negShiftLsB, Const(8 << size)));
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return context.ConditionalSelect(isOutOfRange, Const(op.Type, 0), res);
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}
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else
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{
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Operand isOutOfRange0 = context.ICompareGreaterOrEqual(shiftLsB, Const(8 << size));
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Operand isOutOfRangeN = context.ICompareGreaterOrEqual(negShiftLsB, Const(8 << size));
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// Also zero if shift is too negative, but value was positive.
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isOutOfRange0 = context.BitwiseOr(isOutOfRange0, context.BitwiseAnd(isOutOfRangeN, context.ICompareGreaterOrEqual(op, Const(op.Type, 0))));
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Operand min = (op.Type == OperandType.I64) ? Const(-1L) : Const(-1);
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return context.ConditionalSelect(isOutOfRange0, Const(op.Type, 0), context.ConditionalSelect(isOutOfRangeN, min, res));
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}
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}
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[Flags]
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private enum ShrImmSaturatingNarrowFlags
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{
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Scalar = 1 << 0,
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SignedSrc = 1 << 1,
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SignedDst = 1 << 2,
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Round = 1 << 3,
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ScalarSxSx = Scalar | SignedSrc | SignedDst,
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ScalarSxZx = Scalar | SignedSrc,
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ScalarZxZx = Scalar,
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VectorSxSx = SignedSrc | SignedDst,
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VectorSxZx = SignedSrc,
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VectorZxZx = 0
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}
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private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags)
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{
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EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.Round | flags);
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}
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private static void EmitShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
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bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
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bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
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bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0;
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if (scalar)
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{
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// TODO: Support scalar operation.
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throw new NotImplementedException();
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}
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int shift = GetImmShr(op);
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long roundConst = 1L << (shift - 1);
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EmitVectorUnaryNarrowOp32(context, (op1) =>
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{
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if (op.Size <= 1 || !round)
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{
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if (round)
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{
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op1 = context.Add(op1, Const(op1.Type, roundConst));
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}
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op1 = signedSrc ? context.ShiftRightSI(op1, Const(shift)) : context.ShiftRightUI(op1, Const(shift));
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}
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else /* if (op.Size == 2 && round) */
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{
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op1 = EmitShrImm64(context, op1, signedSrc, roundConst, shift); // shift <= 32
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}
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return EmitSatQ(context, op1, 8 << op.Size, signedSrc, signedDst);
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}, signedSrc);
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}
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private static int GetImmShr(OpCode32SimdShImm op)
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{
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return (8 << op.Size) - op.Shift; // Shr amount is flipped.
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}
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// dst64 = (Int(src64, signed) + roundConst) >> shift;
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private static Operand EmitShrImm64(
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ArmEmitterContext context,
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Operand value,
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bool signed,
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long roundConst,
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int shift)
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{
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MethodInfo info = signed
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? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShrImm64))
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: typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShrImm64));
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return context.Call(info, value, Const(roundConst), Const(shift));
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}
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private static Operand EmitSatQ(ArmEmitterContext context, Operand value, int eSize, bool signedSrc, bool signedDst)
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{
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Debug.Assert(eSize <= 32);
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long intMin = signedDst ? -(1L << (eSize - 1)) : 0;
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long intMax = signedDst ? (1L << (eSize - 1)) - 1 : (1L << eSize) - 1;
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Operand gt = signedSrc
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? context.ICompareGreater(value, Const(value.Type, intMax))
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: context.ICompareGreaterUI(value, Const(value.Type, intMax));
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Operand lt = signedSrc
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? context.ICompareLess(value, Const(value.Type, intMin))
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: context.ICompareLessUI(value, Const(value.Type, intMin));
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value = context.ConditionalSelect(gt, Const(value.Type, intMax), value);
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value = context.ConditionalSelect(lt, Const(value.Type, intMin), value);
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Operand lblNoSat = Label();
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context.BranchIfFalse(lblNoSat, context.BitwiseOr(gt, lt));
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SetFpFlag(context, FPState.QcFlag, Const(1));
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context.MarkLabel(lblNoSat);
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return value;
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}
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}
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}
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