mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-11 15:56:40 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
20 lines
No EOL
526 B
C#
20 lines
No EOL
526 B
C#
using ChocolArm64.Instructions;
|
|
|
|
namespace ChocolArm64.Decoders
|
|
{
|
|
class OpCode32AluRsImm : OpCode32Alu
|
|
{
|
|
public int Rm { get; private set; }
|
|
public int Imm { get; private set; }
|
|
|
|
public ShiftType ShiftType { get; private set; }
|
|
|
|
public OpCode32AluRsImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
|
{
|
|
Rm = (opCode >> 0) & 0xf;
|
|
Imm = (opCode >> 7) & 0x1f;
|
|
|
|
ShiftType = (ShiftType)((opCode >> 5) & 3);
|
|
}
|
|
}
|
|
} |