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Ryujinx/ARMeilleure/Translation
Wunk 45ce540b9b
ARMeilleure: Add gfni acceleration (#3669)
* ARMeilleure: Add `GFNI` detection

This is intended for utilizing the `gf2p8affineqb` instruction

* ARMeilleure: Add `gf2p8affineqb`

Not using the VEX or EVEX-form of this instruction is intentional. There
are `GFNI`-chips that do not support AVX(so no VEX encoding) such as
Tremont(Lakefield) chips as well as Jasper Lake.

13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)

13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)

* ARMeilleure: Add `gfni` acceleration of `Rbit_V`

Passes all `Rbit_V*` unit tests on my `i9-11900k`

* ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V`

Also added a fast-path for when the shift amount is greater than the
size of the element.

* ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V`

* ARMeilleure: Increment InternalVersion

* ARMeilleure: Fix Intrinsic and Assembler Table alignment

`gf2p8affineqb` is the longest instruction name I know of. It shouldn't
get any wider than this.

* ARMeilleure: Remove SSE2+SHA requirement for GFNI

* ARMeilleure Add `X86GetGf2p8LogicalShiftLeft`

Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction.

* ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
2022-10-02 11:17:19 +02:00
..
Cache misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
PTC ARMeilleure: Add gfni acceleration (#3669) 2022-10-02 11:17:19 +02:00
ArmEmitterContext.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
Compiler.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
CompilerContext.cs
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Implement some 32-bit Thumb instructions (#3614) 2022-08-25 09:59:34 +00:00
DelegateHelper.cs
DelegateInfo.cs PPTC Follow-up. (#1712) 2020-12-17 20:32:09 +01:00
Delegates.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00
DispatcherFunction.cs Add multi-level function table (#2228) 2021-05-29 18:06:28 -03:00
Dominance.cs
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs
IntervalTree.cs Optimize kernel memory block lookup and consolidate RBTree implementations (#3410) 2022-08-26 18:21:48 +00:00
RegisterToLocal.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
RegisterUsage.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
RejitRequest.cs
SsaConstruction.cs Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145) 2022-02-22 10:32:10 -03:00
SsaDeconstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
TranslatedFunction.cs Add inlined on translation call counting (#2190) 2021-04-18 23:43:53 +02:00
Translator.cs Clean up rejit queue (#2751) 2022-09-08 20:14:08 -03:00
TranslatorCache.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
TranslatorQueue.cs Clean up rejit queue (#2751) 2022-09-08 20:14:08 -03:00
TranslatorStubs.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00