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https://github.com/Ryujinx/Ryujinx.git
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9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
230 lines
12 KiB
C#
230 lines
12 KiB
C#
#define Mul
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Mul")] // Tested: second half of 2018.
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public sealed class CpuTestMul : CpuTest
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{
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#if Mul
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private const int RndCnt = 2;
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[Test, Pairwise, Description("MADD <Xd>, <Xn>, <Xm>, <Xa>")]
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public void Madd_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MADD <Wd>, <Wn>, <Wm>, <Wa>")]
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public void Madd_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa)
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{
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uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MSUB <Xd>, <Xn>, <Xm>, <Xa>")]
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public void Msub_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MSUB <Wd>, <Wn>, <Wm>, <Wa>")]
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public void Msub_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa)
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{
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uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Smaddl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("UMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Umaddl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Smsubl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("UMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Umsubl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
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{
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uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("SMULH <Xd>, <Xn>, <Xm>")]
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public void Smulh_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm)
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{
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uint Opcode = 0x9B407C00; // SMULH X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("UMULH <Xd>, <Xn>, <Xm>")]
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public void Umulh_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm)
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{
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uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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