1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-11-13 09:16:41 +00:00
Ryujinx/ARMeilleure/IntermediateRepresentation
gdkchan 9878fc2d3c
Implement inline memory load/store exclusive and ordered (#1413)
* Implement inline memory load/store exclusive

* Fix missing REX prefix on 8-bits CMPXCHG

* Increment PTC version due to bugfix

* Remove redundant memory checks

* Address PR feedback

* Increment PPTC version
2020-07-30 11:29:28 -03:00
..
BasicBlock.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
IIntrusiveListNode.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
Instruction.cs Implement inline memory load/store exclusive and ordered (#1413) 2020-07-30 11:29:28 -03:00
Intrinsic.cs Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328) 2020-07-13 20:48:14 +10:00
IntrinsicOperation.cs
IntrusiveList.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
MemoryOperand.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
Multiplier.cs
Node.cs Fix Node Uses/Assignments (#1376) 2020-07-13 20:20:07 +10:00
Operand.cs Fix PPTC on Windows 7. (#1369) 2020-07-09 10:45:24 +10:00
OperandHelper.cs Fix PPTC on Windows 7. (#1369) 2020-07-09 10:45:24 +10:00
OperandKind.cs
OperandType.cs
Operation.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
OperationHelper.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
PhiNode.cs
Register.cs
RegisterType.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00