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Ryujinx/ChocolArm64
LDj3SNuD a5ad1e9a06 Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
2018-04-25 23:20:22 -03:00
..
Decoder [CPU] Fix CBZ/CBNZ with 32 bits operands 2018-04-06 17:22:26 -03:00
Events Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store 2018-02-25 22:14:58 -03:00
Exceptions
Instruction Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) 2018-04-25 23:20:22 -03:00
Memory Improvements to audout (#58) 2018-03-15 21:06:24 -03:00
State Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
Translation Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
ABitUtils.cs
AOpCodeTable.cs Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) 2018-04-25 23:20:22 -03:00
AOptimizations.cs Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
AThread.cs Add SvcSetThreadActivity, tweak SignalProcessWideKey, add fmul32i shader instructions and other small fixes 2018-04-19 16:18:30 -03:00
ATranslatedSub.cs [CPU] Speed up translation a little bit 2018-04-11 14:44:03 -03:00
ATranslatedSubType.cs Improve CPU initial translation speeds (#50) 2018-03-04 14:09:59 -03:00
ATranslator.cs [CPU] Speed up translation a little bit 2018-04-11 14:44:03 -03:00
ChocolArm64.csproj