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https://github.com/Ryujinx/Ryujinx.git
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8a7d99cdea
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
176 lines
No EOL
5.4 KiB
C#
176 lines
No EOL
5.4 KiB
C#
using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.State;
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using System.Collections.Generic;
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namespace ChocolArm64.Translation
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{
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class RegisterUsage
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{
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private const long CallerSavedIntRegistersMask = 0x7fL << 9;
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private const long PStateNzcvFlagsMask = 0xfL << 60;
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private const long CallerSavedVecRegistersMask = 0xffffL << 16;
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private RegisterMask[] _inputs;
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private RegisterMask[] _outputs;
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public RegisterUsage(BasicBlock entryBlock, int blocksCount)
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{
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_inputs = new RegisterMask[blocksCount];
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_outputs = new RegisterMask[blocksCount];
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HashSet<BasicBlock> visited = new HashSet<BasicBlock>();
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Stack<BasicBlock> blockStack = new Stack<BasicBlock>();
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List<BasicBlock> postOrderBlocks = new List<BasicBlock>(blocksCount);
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visited.Add(entryBlock);
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blockStack.Push(entryBlock);
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while (blockStack.TryPop(out BasicBlock block))
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{
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if (block.Next != null && visited.Add(block.Next))
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{
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blockStack.Push(block);
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blockStack.Push(block.Next);
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}
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else if (block.Branch != null && visited.Add(block.Branch))
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{
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blockStack.Push(block);
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blockStack.Push(block.Branch);
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}
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else
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{
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postOrderBlocks.Add(block);
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}
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}
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RegisterMask[] cmnOutputMasks = new RegisterMask[blocksCount];
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bool modified;
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bool firstPass = true;
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do
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{
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modified = false;
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for (int blkIndex = postOrderBlocks.Count - 1; blkIndex >= 0; blkIndex--)
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{
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BasicBlock block = postOrderBlocks[blkIndex];
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if (block.Predecessors.Count != 0 && !block.HasStateLoad)
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{
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BasicBlock predecessor = block.Predecessors[0];
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RegisterMask cmnOutputs = predecessor.RegOutputs | cmnOutputMasks[predecessor.Index];
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RegisterMask outputs = _outputs[predecessor.Index];
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for (int pIndex = 1; pIndex < block.Predecessors.Count; pIndex++)
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{
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predecessor = block.Predecessors[pIndex];
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cmnOutputs &= predecessor.RegOutputs | cmnOutputMasks[predecessor.Index];
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outputs |= _outputs[predecessor.Index];
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}
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_inputs[block.Index] |= outputs & ~cmnOutputs;
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if (!firstPass)
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{
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cmnOutputs &= cmnOutputMasks[block.Index];
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}
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if (Exchange(cmnOutputMasks, block.Index, cmnOutputs))
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{
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modified = true;
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}
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outputs |= block.RegOutputs;
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if (Exchange(_outputs, block.Index, _outputs[block.Index] | outputs))
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{
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modified = true;
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}
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}
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else if (Exchange(_outputs, block.Index, block.RegOutputs))
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{
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modified = true;
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}
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}
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firstPass = false;
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}
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while (modified);
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do
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{
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modified = false;
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for (int blkIndex = 0; blkIndex < postOrderBlocks.Count; blkIndex++)
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{
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BasicBlock block = postOrderBlocks[blkIndex];
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RegisterMask inputs = block.RegInputs;
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if (block.Next != null)
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{
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inputs |= _inputs[block.Next.Index];
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}
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if (block.Branch != null)
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{
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inputs |= _inputs[block.Branch.Index];
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}
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inputs &= ~cmnOutputMasks[block.Index];
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if (Exchange(_inputs, block.Index, _inputs[block.Index] | inputs))
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{
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modified = true;
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}
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}
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}
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while (modified);
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}
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private static bool Exchange(RegisterMask[] masks, int blkIndex, RegisterMask value)
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{
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RegisterMask oldValue = masks[blkIndex];
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masks[blkIndex] = value;
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return oldValue != value;
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}
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public RegisterMask GetInputs(BasicBlock entryBlock) => _inputs[entryBlock.Index];
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public RegisterMask GetOutputs(BasicBlock block) => _outputs[block.Index];
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public static long ClearCallerSavedIntRegs(long mask, ExecutionMode mode)
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{
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//TODO: ARM32 support.
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if (mode == ExecutionMode.Aarch64)
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{
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mask &= ~(CallerSavedIntRegistersMask | PStateNzcvFlagsMask);
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}
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return mask;
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}
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public static long ClearCallerSavedVecRegs(long mask, ExecutionMode mode)
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{
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//TODO: ARM32 support.
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if (mode == ExecutionMode.Aarch64)
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{
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mask &= ~CallerSavedVecRegistersMask;
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}
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return mask;
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}
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}
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} |