mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-11 05:26:38 +00:00
7b35ebc64a
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2 |
||
---|---|---|
.. | ||
CodeGen | ||
Common | ||
Decoders | ||
Diagnostics | ||
Instructions | ||
IntermediateRepresentation | ||
Memory | ||
Signal | ||
State | ||
Translation | ||
Allocators.cs | ||
ARMeilleure.csproj | ||
Optimizations.cs | ||
Statistics.cs |