| .. |
|
CpuContext.cs
|
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
|
2022-05-31 16:29:35 -03:00 |
|
CpuTest.cs
|
Ryujinx.Tests.Unicorn: Implement IDisposable (#3794)
|
2022-10-23 23:51:54 +00:00 |
|
CpuTest32.cs
|
Ryujinx.Tests.Unicorn: Implement IDisposable (#3794)
|
2022-10-23 23:51:54 +00:00 |
|
CpuTestAlu.cs
|
|
|
|
CpuTestAlu32.cs
|
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
|
2022-09-13 19:51:40 -03:00 |
|
CpuTestAluBinary.cs
|
|
|
|
CpuTestAluBinary32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestAluImm.cs
|
|
|
|
CpuTestAluImm32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestAluRs.cs
|
|
|
|
CpuTestAluRs32.cs
|
|
|
|
CpuTestAluRx.cs
|
|
|
|
CpuTestBf32.cs
|
|
|
|
CpuTestBfm.cs
|
|
|
|
CpuTestCcmpImm.cs
|
|
|
|
CpuTestCcmpReg.cs
|
|
|
|
CpuTestCsel.cs
|
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
|
2018-11-01 01:22:09 -03:00 |
|
CpuTestMisc.cs
|
|
|
|
CpuTestMisc32.cs
|
|
|
|
CpuTestMov.cs
|
|
|
|
CpuTestMul.cs
|
|
|
|
CpuTestMul32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestSimd.cs
|
Implement CPU FCVT Half <-> Double conversion variants (#3439)
|
2022-07-06 13:40:31 +02:00 |
|
CpuTestSimd32.cs
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
2022-09-09 21:47:38 -03:00 |
|
CpuTestSimdCrypto.cs
|
|
|
|
CpuTestSimdCrypto32.cs
|
|
|
|
CpuTestSimdCvt.cs
|
Implement FCVTNS (Scalar GP) (#2953)
|
2022-01-19 22:21:44 -03:00 |
|
CpuTestSimdCvt32.cs
|
A32: Implement VCVTT, VCVTB (#3710)
|
2022-10-19 02:36:04 +02:00 |
|
CpuTestSimdExt.cs
|
|
|
|
CpuTestSimdFcond.cs
|
|
|
|
CpuTestSimdFmov.cs
|
|
|
|
CpuTestSimdImm.cs
|
|
|
|
CpuTestSimdIns.cs
|
Add a new JIT compiler for CPU code (#693)
|
2019-08-08 21:56:22 +03:00 |
|
CpuTestSimdLogical32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestSimdMemory32.cs
|
Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)
|
2022-09-13 08:24:09 +02:00 |
|
CpuTestSimdMov32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestSimdReg.cs
|
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
2021-01-04 23:45:54 +01:00 |
|
CpuTestSimdReg32.cs
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
2022-09-09 21:47:38 -03:00 |
|
CpuTestSimdRegElem.cs
|
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
|
2021-03-25 23:33:32 +01:00 |
|
CpuTestSimdRegElem32.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestSimdRegElemF.cs
|
|
|
|
CpuTestSimdShImm.cs
|
|
|
|
CpuTestSimdShImm32.cs
|
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
|
2022-09-09 21:47:38 -03:00 |
|
CpuTestSimdTbl.cs
|
|
|
|
CpuTestSystem.cs
|
|
|
|
CpuTestT32Alu.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestT32Flow.cs
|
T32: Implement B, B.cond, BL, BLX (#3155)
|
2022-03-04 23:05:08 +01:00 |
|
CpuTestT32Mem.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
CpuTestThumb.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
PrecomputedMemoryThumbTestCase.cs
|
Removed unused usings. (#3593)
|
2022-08-18 18:04:54 +02:00 |
|
PrecomputedThumbTestCase.cs
|
T32: Implement ALU (shifted register) instructions (#3135)
|
2022-02-22 19:11:28 -03:00 |
