mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-18 11:36:41 +00:00
db45688aa8
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions * PPTC version * Fix VQADD/VQSUB * Improve MRC/MCR handling and exception messages In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
318 lines
12 KiB
C#
318 lines
12 KiB
C#
#define SimdShImm32
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdShImm32")]
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public sealed class CpuTestSimdShImm32 : CpuTest32
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{
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#if SimdShImm32
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#region "ValueSource (Types)"
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Vshr_Imm_SU8_()
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{
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return new uint[]
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{
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0xf2880010u, // VSHR.S8 D0, D0, #8
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0xf2880110u, // VSRA.S8 D0, D0, #8
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0xf2880210u, // VRSHR.S8 D0, D0, #8
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0xf2880310u // VRSRA.S8 D0, D0, #8
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};
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}
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private static uint[] _Vshr_Imm_SU16_()
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{
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return new uint[]
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{
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0xf2900010u, // VSHR.S16 D0, D0, #16
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0xf2900110u, // VSRA.S16 D0, D0, #16
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0xf2900210u, // VRSHR.S16 D0, D0, #16
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0xf2900310u // VRSRA.S16 D0, D0, #16
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};
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}
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private static uint[] _Vshr_Imm_SU32_()
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{
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return new uint[]
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{
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0xf2a00010u, // VSHR.S32 D0, D0, #32
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0xf2a00110u, // VSRA.S32 D0, D0, #32
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0xf2a00210u, // VRSHR.S32 D0, D0, #32
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0xf2a00310u // VRSRA.S32 D0, D0, #32
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};
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}
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private static uint[] _Vshr_Imm_SU64_()
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{
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return new uint[]
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{
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0xf2800190u, // VSRA.S64 D0, D0, #64
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0xf2800290u, // VRSHR.S64 D0, D0, #64
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0xf2800090u // VSHR.S64 D0, D0, #64
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};
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}
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private static uint[] _Vqshrn_Vqrshrn_Vrshrn_Imm_()
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{
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return new uint[]
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{
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0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN)
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0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN)
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0xf2800850u // VMOV.I16 Q0, #0 (immediate value changes it into RSHRN)
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};
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}
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private static uint[] _Vqshrun_Vqrshrun_Imm_()
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{
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return new uint[]
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{
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0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN)
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0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
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};
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntShiftImm = 2;
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[Test, Pairwise]
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public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
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[Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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uint imm6 = 16 - shiftImm;
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Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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uint imm6 = 32 - shiftImm;
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Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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uint imm6 = 64 - shiftImm;
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Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
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}
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[Test, Pairwise]
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public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
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[Range(0u, 3u)] uint rd,
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[Range(0u, 3u)] uint rm,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong b,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
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[Values] bool u,
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[Values] bool q)
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{
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uint imm6 = 64 - shiftImm;
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Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
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}
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private void Vshr_Imm_SU(uint opcode, uint rd, uint rm, ulong z, ulong b, uint imm6, bool u, bool q)
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{
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if (u)
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{
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opcode |= 1 << 24;
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}
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if (q)
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{
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opcode |= 1 << 6;
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rd >>= 1; rd <<= 1;
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rm >>= 1; rm <<= 1;
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}
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= (imm6 & 0x3f) << 16;
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")]
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public void Vshl_Imm([Values(0u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u, 3u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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uint opcode = 0xf2800510u; // VORR.I32 D0, #0 (immediate value changes it into SHL)
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if (q)
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{
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opcode |= 1 << 6;
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rm <<= 1;
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rd <<= 1;
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}
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSHRN.<size> <Vd>, <Vm>, #<imm>")]
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public void Vshrn_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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{
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uint opcode = 0xf2800810u; // VMOV.I16 D0, #0 (immediate value changes it into SHRN)
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource("_Vqshrn_Vqrshrn_Vrshrn_Imm_")] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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{
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16);
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if (u)
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{
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opcode |= 1u << 24;
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}
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
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}
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[Test, Pairwise]
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public void Vqshrun_Vqrshrun_Imm([ValueSource("_Vqshrun_Vqrshrun_Imm_")] uint opcode,
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[Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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{
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
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}
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#endif
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}
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}
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