mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-10 20:46:43 +00:00
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
19 lines
544 B
C#
19 lines
544 B
C#
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCode32SimdRegElemLong : OpCode32SimdRegElem
|
|
{
|
|
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
Q = false;
|
|
F = false;
|
|
|
|
RegisterSize = RegisterSize.Simd64;
|
|
|
|
// (Vd & 1) != 0 || Size == 3 are also invalid, but they are checked on encoding.
|
|
if (Size == 0)
|
|
{
|
|
Instruction = InstDescriptor.Undefined;
|
|
}
|
|
}
|
|
}
|
|
}
|