1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-11-13 15:26:39 +00:00
Ryujinx/ChocolArm64
LDj3SNuD c106ae9944 Add Tbl_V Sse opt. with Tests. (#651)
* Add v4, v5, v30, v31 required for Tbl_V Tests.

* Add Tests for Tbl_V.

* Add Tbl_V Sse opt..

* Nit.

* Small opt. on comparison constant vector.

* Nit.

* Add EmitLd/Stvectmp2/3.

* Nit.
2019-03-23 15:50:19 -03:00
..
Decoders Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 2019-02-23 20:52:48 -03:00
Events Optimize address translation and write tracking on the MMU (#571) 2019-02-24 18:24:35 +11:00
Instructions Add Tbl_V Sse opt. with Tests. (#651) 2019-03-23 15:50:19 -03:00
Memory Optimize address translation and write tracking on the MMU (#571) 2019-02-24 18:24:35 +11:00
State ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
Translation Add Tbl_V Sse opt. with Tests. (#651) 2019-03-23 15:50:19 -03:00
ChocolArm64.csproj ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
CpuThread.cs ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
OpCodeTable.cs Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 2019-02-23 20:52:48 -03:00
Optimizations.cs Misc. CPU optimizations (#575) 2019-02-28 13:03:31 +11:00