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CryptoHelper.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitAlu.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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InstEmitAlu32.cs
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Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
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2020-12-17 20:43:41 +01:00 |
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InstEmitAluHelper.cs
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Clear JIT cache on exit (#1518)
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2020-12-16 17:07:42 -03:00 |
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InstEmitBfm.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitCcmp.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitCsel.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitDiv.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitException.cs
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IPC refactor part 1: Use explicit separate threads to process requests (#1447)
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2020-09-22 14:50:40 +10:00 |
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InstEmitException32.cs
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IPC refactor part 1: Use explicit separate threads to process requests (#1447)
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2020-09-22 14:50:40 +10:00 |
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InstEmitFlow.cs
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Generalize tail continues (#1298)
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2020-06-18 13:37:21 +10:00 |
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InstEmitFlow32.cs
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Generalize tail continues (#1298)
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2020-06-18 13:37:21 +10:00 |
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InstEmitFlowHelper.cs
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Add multi-level function table (#2228)
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2021-05-29 18:06:28 -03:00 |
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InstEmitHash.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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InstEmitHash32.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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InstEmitHashHelper.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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InstEmitHelper.cs
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Clear JIT cache on exit (#1518)
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2020-12-16 17:07:42 -03:00 |
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InstEmitMemory.cs
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Fold constant offsets and group constant addresses (#2285)
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2021-05-13 21:26:57 +02:00 |
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InstEmitMemory32.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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InstEmitMemoryEx.cs
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Implement PRFM (register variant) as NOP (#1956)
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2021-01-26 16:09:27 +11:00 |
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InstEmitMemoryEx32.cs
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Implement inline memory load/store exclusive and ordered (#1413)
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2020-07-30 11:29:28 -03:00 |
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InstEmitMemoryExHelper.cs
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Validate CPU virtual addresses on access (#1987)
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2021-02-16 19:04:19 +01:00 |
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InstEmitMemoryHelper.cs
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Add multi-level function table (#2228)
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2021-05-29 18:06:28 -03:00 |
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InstEmitMove.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitMul.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitMul32.cs
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Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
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2020-12-17 20:43:41 +01:00 |
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InstEmitSimdArithmetic.cs
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Improve accuracy of reciprocal step instructions (#2305)
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2021-05-24 20:20:07 +10:00 |
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InstEmitSimdArithmetic32.cs
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Implement VCNT instruction (#1963)
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2021-02-22 16:26:13 +01:00 |
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InstEmitSimdCmp.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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InstEmitSimdCmp32.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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InstEmitSimdCrypto.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdCrypto32.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdCvt.cs
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CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)
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2020-11-18 19:35:54 +01:00 |
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InstEmitSimdCvt32.cs
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CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
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2020-12-16 20:27:15 -03:00 |
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InstEmitSimdHash.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdHelper.cs
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Add BIC/ORR Vd.T, #imm fast path (#2279)
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2021-05-20 09:09:17 -03:00 |
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InstEmitSimdHelper32.cs
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CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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2021-01-04 23:45:54 +01:00 |
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InstEmitSimdLogical.cs
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Add BIC/ORR Vd.T, #imm fast path (#2279)
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2021-05-20 09:09:17 -03:00 |
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InstEmitSimdLogical32.cs
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Implement VORN (register) Arm32 instruction (#2396)
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2021-06-23 23:21:23 +02:00 |
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InstEmitSimdMemory.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstEmitSimdMemory32.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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InstEmitSimdMove.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSimdMove32.cs
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Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
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2020-08-13 02:34:02 -03:00 |
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InstEmitSimdShift.cs
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Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
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2020-07-13 21:08:47 +10:00 |
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InstEmitSimdShift32.cs
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Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
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2020-10-13 22:41:33 +02:00 |
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InstEmitSystem.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
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InstEmitSystem32.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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InstName.cs
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Implement VORN (register) Arm32 instruction (#2396)
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2021-06-23 23:21:23 +02:00 |
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NativeInterface.cs
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Add multi-level function table (#2228)
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2021-05-29 18:06:28 -03:00 |
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SoftFallback.cs
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Implement VCNT instruction (#1963)
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2021-02-22 16:26:13 +01:00 |
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SoftFloat.cs
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Add Profiled Persistent Translation Cache. (#769)
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2020-06-16 20:28:02 +02:00 |
