LDj3SNuD dc0adb533d PPTC & Pool Enhancements. (#1968) ... * PPTC & Pool Enhancements. * Avoid buffer allocations in CodeGenContext.GetCode(). Avoid stream allocations in PTC.PtcInfo. Refactoring/nits. * Use XXHash128, for Ptc.Load & Ptc.Save, x10 faster than Md5. * Why not a nice Span. * Added a simple PtcFormatter library for deserialization/serialization, which does not require reflection, in use at PtcJumpTable and PtcProfiler; improves maintainability and simplicity/readability of affected code. * Nits. * Revert #1987. * Revert "Revert #1987." This reverts commit 998be765cf.		2021-02-22 03:23:48 +01:00
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Aarch32Mode.cs
ExecutionContext.cs	IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458)	2020-12-02 00:23:43 +01:00
ExecutionMode.cs	PPTC & Pool Enhancements. (#1968)	2021-02-22 03:23:48 +01:00
FPCR.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPException.cs
FPRoundingMode.cs
FPSR.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPState.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
FPType.cs
InstExceptionEventArgs.cs
InstUndefinedEventArgs.cs
NativeContext.cs	Implement inline memory load/store exclusive and ordered (#1413)	2020-07-30 11:29:28 -03:00
PState.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
RegisterAlias.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
RegisterConsts.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
V128.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00