2018-03-27 00:04:16 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-03-14 23:26:19 +00:00
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#include "cluster.h"
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#include "i2c.h"
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#include "clock.h"
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#include "util.h"
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#include "pmc.h"
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#include "t210.h"
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void _cluster_enable_power()
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{
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u8 tmp;
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if (i2c_recv_buf_small(&tmp, 1, I2C_5, 0x3C, 0x40))
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{
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tmp &= 0xDFu;
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i2c_send_byte(I2C_5, 0x3C, 0x40, tmp);
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}
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i2c_send_byte(I2C_5, 0x3C, 0x3B, 0x09);
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//Enable cores power.
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i2c_send_byte(I2C_5, 0x1B, 0x02, 0x20);
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i2c_send_byte(I2C_5, 0x1B, 0x03, 0x8D);
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i2c_send_byte(I2C_5, 0x1B, 0x00, 0xB7);
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i2c_send_byte(I2C_5, 0x1B, 0x01, 0xB7);
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}
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int _cluster_pmc_enable_partition(u32 part, u32 toggle)
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{
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//Check if the partition has already been turned on.
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if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
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return 0;
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u32 i = 5001;
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while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
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{
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sleep(1);
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i--;
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if (i < 1)
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return 0;
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}
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PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100;
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i = 5001;
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while (i > 0)
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{
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if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
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break;
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sleep(1);
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i--;
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}
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return 1;
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}
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void cluster_enable_cpu0(u32 entry)
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{
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//Set ACTIVE_CLUSER to FAST.
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FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
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_cluster_enable_power();
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if (!(CLOCK(0xE0) & 0x40000000))
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{
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CLOCK(0x518) &= 0xFFFFFFF7;
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sleep(2);
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CLOCK(0xE4) = CLOCK(0xE4) & 0xFFFBFFFF | 0x40000;
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CLOCK(0xE0) = 0x40404E02;
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}
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while (!(CLOCK(0xE0) & 0x8000000))
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;
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CLOCK(0x3B4) = CLOCK(0x3B4) & 0x1FFFFF00 | 6;
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CLOCK(0x360) = CLOCK(0x360) & 0xFFFFFFF7 | 8;
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CLOCK(0x20) = 0x20008888;
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CLOCK(0x24) = 0x80000000;
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CLOCK(0x440) = 1;
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clock_enable_coresight();
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CLOCK(0x388) = CLOCK(0x388) & 0xFFFFE000;
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//Enable CPU rail.
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_cluster_pmc_enable_partition(1, 0);
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//Enable cluster 0 non-CPU.
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_cluster_pmc_enable_partition(0x8000, 15);
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//Enable CE0.
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_cluster_pmc_enable_partition(0x4000, 14);
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//Request and wait for RAM repair.
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FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
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while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
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;
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EXCP_VEC(0x100) = 0;
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//Set reset vectors.
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SB(SB_AA64_RESET_LOW) = entry | 1;
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SB(SB_AA64_RESET_HIGH) = 0;
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//Non-secure reset vector write disable.
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SB(SB_CSR_0) = 2;
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//Until here the CPU was in reset, this kicks execution.
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x411F000F;
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}
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