From 0862cb1e7e7b9d9a46edebd55436762ac45c8801 Mon Sep 17 00:00:00 2001 From: "ctcaer@gmail.com" Date: Sat, 6 Jul 2019 22:16:42 +0300 Subject: [PATCH] [HOS] Fixed 6.0.x/6.1.0 stock --- bootloader/hos/pkg1.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/bootloader/hos/pkg1.c b/bootloader/hos/pkg1.c index 397014b..ae59892 100644 --- a/bootloader/hos/pkg1.c +++ b/bootloader/hos/pkg1.c @@ -72,15 +72,15 @@ PATCHSET_DEF(_secmon_6_patchset, { 0xDC8 + 0x820, _NOP() }, //package2 structure. { 0xDC8 + 0x82C, _NOP() }, //Version. { 0xDC8 + 0xE90, _NOP() }, //Header signature. - { 0xDC8 + 0x112C, _NOP() }, //Sections SHA2. + { 0xDC8 + 0x112C, _NOP() } //Sections SHA2. // Fix sleep mode for debug. - { 0x1A68 + 0x3854, 0x94000E45 }, //gpio_config_for_uart. - { 0x1A68 + 0x3858, 0x97FFFC0F }, //clkrst_reboot_uarta. - { 0x1A68 + 0x385C, 0x52A00021 }, //MOV W1, #0x10000 ; baudrate. - { 0x1A68 + 0x3860, 0x2A1F03E0 }, //MOV W0, WZR ; uart_port -> A. - { 0x1A68 + 0x3864, 0x72984001 }, //MOVK W1, #0xC200 ; baudrate. - { 0x1A68 + 0x3868, 0x94000C8C }, //uart_configure. - { 0x1A68 + 0x3A6C, _NOP() } // warmboot UARTA cfg. + // { 0x1A68 + 0x3854, 0x94000E45 }, //gpio_config_for_uart. + // { 0x1A68 + 0x3858, 0x97FFFC0F }, //clkrst_reboot_uarta. + // { 0x1A68 + 0x385C, 0x52A00021 }, //MOV W1, #0x10000 ; baudrate. + // { 0x1A68 + 0x3860, 0x2A1F03E0 }, //MOV W0, WZR ; uart_port -> A. + // { 0x1A68 + 0x3864, 0x72984001 }, //MOVK W1, #0xC200 ; baudrate. + // { 0x1A68 + 0x3868, 0x94000C8C }, //uart_configure. + // { 0x1A68 + 0x3A6C, _NOP() } // warmboot UARTA cfg. ); PATCHSET_DEF(_secmon_620_patchset, @@ -88,15 +88,15 @@ PATCHSET_DEF(_secmon_620_patchset, { 0xDC8 + 0x604, _NOP() }, //package2 structure. { 0xDC8 + 0x610, _NOP() }, //Version. { 0xDC8 + 0xC74, _NOP() }, //Header signature. - { 0xDC8 + 0xF10, _NOP() }, //Sections SHA2. + { 0xDC8 + 0xF10, _NOP() } //Sections SHA2. // Fix sleep mode for debug. - { 0x2AC8 + 0x3854, 0x94000F42 }, //gpio_config_for_uart. - { 0x2AC8 + 0x3858, 0x97FFFC0F }, //clkrst_reboot_uarta. - { 0x2AC8 + 0x385C, 0x52A00021 }, //MOV W1, #0x10000 ; baudrate. - { 0x2AC8 + 0x3860, 0x2A1F03E0 }, //MOV W0, WZR ; uart_port -> A. - { 0x2AC8 + 0x3864, 0x72984001 }, //MOVK W1, #0xC200 ; baudrate. - { 0x2AC8 + 0x3868, 0x94000D89 }, //uart_configure. - { 0x2AC8 + 0x3A6C, _NOP() } // warmboot UARTA cfg. + // { 0x2AC8 + 0x3854, 0x94000F42 }, //gpio_config_for_uart. + // { 0x2AC8 + 0x3858, 0x97FFFC0F }, //clkrst_reboot_uarta. + // { 0x2AC8 + 0x385C, 0x52A00021 }, //MOV W1, #0x10000 ; baudrate. + // { 0x2AC8 + 0x3860, 0x2A1F03E0 }, //MOV W0, WZR ; uart_port -> A. + // { 0x2AC8 + 0x3864, 0x72984001 }, //MOVK W1, #0xC200 ; baudrate. + // { 0x2AC8 + 0x3868, 0x94000D89 }, //uart_configure. + // { 0x2AC8 + 0x3A6C, _NOP() } // warmboot UARTA cfg. ); PATCHSET_DEF(_warmboot_1_patchset,