diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c
index 536769b..37ce73d 100644
--- a/bdk/soc/ccplex.c
+++ b/bdk/soc/ccplex.c
@@ -15,6 +15,7 @@
* along with this program. If not, see .
*/
+#include
#include
#include
#include
diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c
index abf3564..e2ca991 100644
--- a/bdk/soc/clock.c
+++ b/bdk/soc/clock.c
@@ -60,22 +60,22 @@ static const clock_t _clock_i2c[] = {
};
static clock_t _clock_se = {
- CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz.
+ CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz. Default: 408MHz. Max: 627.2 MHz.
};
static clock_t _clock_tzram = {
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0
};
static clock_t _clock_host1x = {
- CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz.
+ CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz. Max: 408MHz.
};
static clock_t _clock_tsec = {
- CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz.
+ CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz. Max: 408MHz.
};
static clock_t _clock_nvdec = {
- CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC, CLK_Y_NVDEC, 4, 0 // 408 MHz.
+ CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC, CLK_Y_NVDEC, 4, 0 // 408 MHz. Max: 716.8/979.2MHz.
};
static clock_t _clock_nvjpg = {
- CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG, CLK_Y_NVJPG, 4, 0 // 408 MHz.
+ CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG, CLK_Y_NVJPG, 4, 0 // 408 MHz. Max: 627.2/652.8MHz.
};
static clock_t _clock_sor_safe = {
CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0
@@ -102,7 +102,7 @@ static clock_t _clock_sdmmc_legacy_tm = {
CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66
};
static clock_t _clock_apbdma = {
- CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0
+ CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0 // Max: 204MHz.
};
static clock_t _clock_ahbdma = {
CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, 0
@@ -434,7 +434,7 @@ void clock_enable_pllc(u32 divn)
// Take PLLC out of reset and set basic misc parameters.
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
- ((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
+ ((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x8000 << 4); // PLLC_EXT_FRU.
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
// Disable PLL and IDDQ in case they are on.
@@ -540,9 +540,9 @@ void clock_enable_pllu()
void clock_disable_pllu()
{
- CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M.
- CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x40000000; // Disable PLLU.
- CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~0x20000000; // Enable reference clock.
+ CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M.
+ CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~BIT(30); // Disable PLLU.
+ CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~BIT(29); // Enable reference clock.
}
void clock_enable_utmipll()
@@ -707,10 +707,6 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
*pclock = 25500;
divisor = 30; // 16 div.
break;
- case 40800:
- *pclock = 40800;
- divisor = 18; // 10 div.
- break;
case 50000:
*pclock = 48000;
divisor = 15; // 8.5 div.
@@ -719,6 +715,10 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
*pclock = 51000;
divisor = 14; // 8 div.
break;
+ case 81600: // Originally MMC_HS50 for GC FPGA at 40800 KHz, div 18 (real 10).
+ *pclock = 81600;
+ divisor = 8; // 5 div.
+ break;
case 100000:
source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
*pclock = 99840;
@@ -846,10 +846,10 @@ void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
*pdivisor = 1;
break;
case SDHCI_TIMING_UHS_DDR50:
- *pclock = 40800;
- *pdivisor = 1;
+ *pclock = 81600; // Originally MMC_HS50 for GC FPGA at 40800 KHz, div 1.
+ *pdivisor = 2;
break;
- case SDHCI_TIMING_MMC_HS102: // Actual IO Freq: 99.84 MHz.
+ case SDHCI_TIMING_MMC_DDR100: // Actual IO Freq: 99.84 MHz.
*pclock = 200000;
*pdivisor = 2;
break;
diff --git a/bdk/storage/sdmmc.c b/bdk/storage/sdmmc.c
index f3e6cbc..4ab775a 100644
--- a/bdk/storage/sdmmc.c
+++ b/bdk/storage/sdmmc.c
@@ -1099,6 +1099,7 @@ DPRINTF("[SD] bus speed set to SDR50\n");
storage->csd.busspeed = 50;
break;
}
+/*
case SDHCI_TIMING_UHS_SDR25:
if (access_mode & SD_MODE_UHS_SDR25)
{
@@ -1108,6 +1109,7 @@ DPRINTF("[SD] bus speed set to SDR25\n");
storage->csd.busspeed = 25;
break;
}
+*/
case SDHCI_TIMING_UHS_SDR12:
if (!(access_mode & SD_MODE_UHS_SDR12))
return 0;
@@ -1504,13 +1506,13 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc)
memset(storage, 0, sizeof(sdmmc_storage_t));
storage->sdmmc = sdmmc;
- if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS102, SDMMC_POWER_SAVE_DISABLE))
+ if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_DDR100, SDMMC_POWER_SAVE_DISABLE))
return 0;
DPRINTF("[gc] after init\n");
usleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor);
- if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS102, MMC_SEND_TUNING_BLOCK_HS200))
+ if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_DDR100, MMC_SEND_TUNING_BLOCK_HS200))
return 0;
DPRINTF("[gc] after tuning\n");
diff --git a/bdk/storage/sdmmc_driver.c b/bdk/storage/sdmmc_driver.c
index de9c689..a20d127 100644
--- a/bdk/storage/sdmmc_driver.c
+++ b/bdk/storage/sdmmc_driver.c
@@ -116,7 +116,7 @@ void sdmmc_save_tap_value(sdmmc_t *sdmmc)
static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
{
const u32 dqs_trim_val = 0x28;
- const u32 tap_values_t210[] = { 4, 0, 3, 0 };
+ const u8 tap_values_t210[4] = { 4, 0, 3, 0 };
u32 tap_val = 0;
@@ -339,7 +339,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
case SDHCI_TIMING_UHS_SDR104:
case SDHCI_TIMING_UHS_SDR82:
case SDHCI_TIMING_UHS_DDR50:
- case SDHCI_TIMING_MMC_HS102:
+ case SDHCI_TIMING_MMC_DDR100:
sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
break;
@@ -687,7 +687,7 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
case SDHCI_TIMING_UHS_SDR50:
case SDHCI_TIMING_UHS_DDR50:
- case SDHCI_TIMING_MMC_HS102:
+ case SDHCI_TIMING_MMC_DDR100:
max = 256;
flag = (4 << 13); // 256 iterations.
break;
@@ -1253,9 +1253,9 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
u16 divisor;
u8 vref_sel = 7;
- const u32 trim_values_t210[] = { 2, 8, 3, 8 };
- const u32 trim_values_t210b01[] = { 14, 13, 15, 13 };
- const u32 *trim_values;
+ const u8 trim_values_t210[4] = { 2, 8, 3, 8 };
+ const u8 trim_values_t210b01[4] = { 14, 13, 15, 13 };
+ const u8 *trim_values;
if (id > SDMMC_4 || id == SDMMC_3)
return 0;
@@ -1306,7 +1306,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
// Set default pad IO trimming configuration.
sdmmc->regs->iospare |= 0x80000; // Enable muxing.
sdmmc->regs->veniotrimctl &= 0xFFFFFFFB; // Set Band Gap VREG to supply DLL.
- sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | (trim_values[sdmmc->id] << 24);
+ sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | ((u32)trim_values[sdmmc->id] << 24);
sdmmc->regs->sdmemcmppadctl =
(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK) | vref_sel;
diff --git a/bdk/storage/sdmmc_driver.h b/bdk/storage/sdmmc_driver.h
index 8128280..43263b8 100644
--- a/bdk/storage/sdmmc_driver.h
+++ b/bdk/storage/sdmmc_driver.h
@@ -206,9 +206,10 @@
#define SDHCI_TIMING_UHS_SDR25 9
#define SDHCI_TIMING_UHS_SDR50 10
#define SDHCI_TIMING_UHS_SDR104 11
-#define SDHCI_TIMING_UHS_SDR82 12 // SDR104 with a 163.2MHz -> 81.6MHz clock.
-#define SDHCI_TIMING_UHS_DDR50 13
-#define SDHCI_TIMING_MMC_HS102 14
+#define SDHCI_TIMING_UHS_DDR50 12
+// SDR104 with a 163.2MHz -> 81.6MHz clock.
+#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
+#define SDHCI_TIMING_MMC_DDR100 14 // GC ASIC.
#define SDHCI_CAN_64BIT BIT(28)