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bdk: sdmmc: add UHS DDR50 support
But disable it by default in the auto selection.
This commit is contained in:
parent
76a5facbc3
commit
25be98b7e3
2 changed files with 26 additions and 19 deletions
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@ -1038,7 +1038,7 @@ DPRINTF("[SD] power limit defaulted to 720 mW\n");
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}
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}
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static int _sd_storage_enable_highspeed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf)
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static int _sd_storage_set_card_bus_speed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf)
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{
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if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_ACCESS, hs_type))
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return 0;
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@ -1115,31 +1115,34 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
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break;
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}
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/*
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case SDHCI_TIMING_UHS_DDR50:
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if (access_mode & SD_MODE_UHS_DDR50)
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{
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type = SDHCI_TIMING_UHS_DDR50;
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hs_type = UHS_DDR50_BUS_SPEED;
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DPRINTF("[SD] setting bus speed to DDR50\n");
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storage->csd.busspeed = 50;
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break;
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}
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*/
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case SDHCI_TIMING_UHS_SDR25:
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if (access_mode & SD_MODE_UHS_SDR25)
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{
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type = SDHCI_TIMING_UHS_SDR25;
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hs_type = UHS_SDR25_BUS_SPEED;
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DPRINTF("[SD] bus speed set to SDR25\n");
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DPRINTF("[SD] setting bus speed to SDR25\n");
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storage->csd.busspeed = 25;
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break;
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}
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*/
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case SDHCI_TIMING_UHS_SDR12:
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if (!(access_mode & SD_MODE_UHS_SDR12))
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return 0;
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type = SDHCI_TIMING_UHS_SDR12;
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hs_type = UHS_SDR12_BUS_SPEED;
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DPRINTF("[SD] bus speed set to SDR12\n");
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storage->csd.busspeed = 12;
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break;
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default:
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return 0;
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break;
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DPRINTF("[SD] bus speed defaulted to SDR12\n");
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storage->csd.busspeed = 12;
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return 1;
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}
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if (!_sd_storage_enable_highspeed(storage, hs_type, buf))
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// Setup and set selected card and bus speed.
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if (!_sd_storage_set_card_bus_speed(storage, hs_type, buf))
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return 0;
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DPRINTF("[SD] card accepted UHS\n");
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@ -1169,7 +1172,7 @@ static int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
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if (!(access_mode & SD_MODE_HIGH_SPEED))
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return 1;
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if (!_sd_storage_enable_highspeed(storage, HIGH_SPEED_BUS_SPEED, buf))
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if (!_sd_storage_set_card_bus_speed(storage, HIGH_SPEED_BUS_SPEED, buf))
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return 0;
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if (!_sdmmc_storage_check_status(storage))
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@ -108,7 +108,7 @@ void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width)
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void sdmmc_save_tap_value(sdmmc_t *sdmmc)
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{
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sdmmc->venclkctl_tap = sdmmc->regs->venclkctl >> 16;
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sdmmc->venclkctl_tap = (sdmmc->regs->venclkctl & 0xFF0000) >> 16;
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sdmmc->venclkctl_set = 1;
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}
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@ -331,7 +331,6 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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case SDHCI_TIMING_UHS_SDR50: // T210 Errata: the host must be set to SDR104 to WAR a CRC issue.
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case SDHCI_TIMING_UHS_SDR104:
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case SDHCI_TIMING_UHS_SDR82:
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case SDHCI_TIMING_UHS_DDR50:
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case SDHCI_TIMING_MMC_HS100:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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@ -351,6 +350,11 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR12_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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case SDHCI_TIMING_UHS_DDR50:
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sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_DDR50_BUS_SPEED;
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sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
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break;
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}
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_sdmmc_commit_changes(sdmmc);
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@ -664,7 +668,6 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
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switch (type)
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{
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case SDHCI_TIMING_MMC_HS200:
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR104:
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case SDHCI_TIMING_UHS_SDR82:
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num_iter = 128;
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@ -672,12 +675,13 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
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break;
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case SDHCI_TIMING_UHS_SDR50:
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case SDHCI_TIMING_UHS_DDR50:
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case SDHCI_TIMING_UHS_DDR50: // HW tuning is not supported on DDR modes. But it sets tap to 0 which is proper.
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case SDHCI_TIMING_MMC_HS100:
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num_iter = 256;
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flag = (4 << 13); // 256 iterations.
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break;
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case SDHCI_TIMING_MMC_HS400:
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case SDHCI_TIMING_UHS_SDR12:
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case SDHCI_TIMING_UHS_SDR25:
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return 1;
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