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bdk: display: deduplicate array size macro
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CTCaer
parent
bd55a3e756
commit
28eb3f4bcd
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@ -448,26 +448,26 @@ void display_init()
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clock_enable_plld(3, 20, true, tegra_t210);
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// Setup Display Interface initial window configuration.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, CFG_SIZE(_di_dc_setup_win_config));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, ARRAY_SIZE(_di_dc_setup_win_config));
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// Setup dsi init sequence packets.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, CFG_SIZE(_di_dsi_init_irq_pkt_config0));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config0, ARRAY_SIZE(_di_dsi_init_irq_pkt_config0));
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if (tegra_t210)
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DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0;
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else
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DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0;
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, CFG_SIZE(_di_dsi_init_irq_pkt_config1));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_irq_pkt_config1, ARRAY_SIZE(_di_dsi_init_irq_pkt_config1));
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// Reset pad trimmers for T210B01.
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if (!tegra_t210)
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, CFG_SIZE(_di_dsi_init_pads_t210b01));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, ARRAY_SIZE(_di_dsi_init_pads_t210b01));
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// Setup init sequence packets and timings.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config2, CFG_SIZE(_di_dsi_init_timing_pkt_config2));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config2, ARRAY_SIZE(_di_dsi_init_timing_pkt_config2));
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pwrctrl_config, CFG_SIZE(_di_dsi_init_timing_pwrctrl_config));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pwrctrl_config, ARRAY_SIZE(_di_dsi_init_timing_pwrctrl_config));
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; // DSI_THSPREPR: 1 : 3.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config3, CFG_SIZE(_di_dsi_init_timing_pkt_config3));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_timing_pkt_config3, ARRAY_SIZE(_di_dsi_init_timing_pkt_config3));
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usleep(10000);
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// Enable LCD Reset.
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@ -537,7 +537,7 @@ void display_init()
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break;
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case PANEL_JDI_XXX062M:
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, CFG_SIZE(_di_dsi_panel_init_config_jdi));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, ARRAY_SIZE(_di_dsi_panel_init_config_jdi));
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_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
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break;
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@ -580,18 +580,18 @@ void display_init()
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// Finalize DSI init packet sequence configuration.
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DSI(_DSIREG(DSI_PAD_CONTROL_1)) = 0;
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DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603;
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, CFG_SIZE(_di_dsi_init_seq_pkt_final_config));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, ARRAY_SIZE(_di_dsi_init_seq_pkt_final_config));
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// Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate.
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
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// Set DSI mode.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_mode_config, CFG_SIZE(_di_dsi_mode_config));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_mode_config, ARRAY_SIZE(_di_dsi_mode_config));
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usleep(10000);
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// Calibrate display communication pads.
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u32 loops = tegra_t210 ? 1 : 2; // Calibrate pads 2 times on T210B01.
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, CFG_SIZE(_di_mipi_pad_cal_config));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, ARRAY_SIZE(_di_mipi_pad_cal_config));
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for (u32 i = 0; i < loops; i++)
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{
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// Set MIPI bias pad config.
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@ -601,22 +601,22 @@ void display_init()
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// Set pad trimmers and set MIPI DSI cal offsets.
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if (tegra_t210)
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{
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, CFG_SIZE(_di_dsi_pad_cal_config_t210));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_offsets_config_t210));
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}
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else
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{
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, CFG_SIZE(_di_dsi_pad_cal_config_t210b01));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, CFG_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, ARRAY_SIZE(_di_dsi_pad_cal_config_t210b01));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_offsets_config_t210b01, ARRAY_SIZE(_di_mipi_dsi_cal_offsets_config_t210b01));
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}
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// Reset all MIPI cal offsets and start calibration.
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_start_dsi_cal_config, CFG_SIZE(_di_mipi_start_dsi_cal_config));
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exec_cfg((u32 *)MIPI_CAL_BASE, _di_mipi_start_dsi_cal_config, ARRAY_SIZE(_di_mipi_start_dsi_cal_config));
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}
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usleep(10000);
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// Enable video display controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, CFG_SIZE(_di_dc_video_enable_config));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, ARRAY_SIZE(_di_dc_video_enable_config));
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}
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void display_backlight_pwm_init()
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@ -722,7 +722,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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// De-initialize video controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, CFG_SIZE(_di_dc_video_disable_config));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, ARRAY_SIZE(_di_dc_video_disable_config));
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// Set DISP1 clock source, parent clock and DSI/PCLK to low power mode.
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// T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz)
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@ -730,7 +730,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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clock_enable_plld(3, 20, true, hw_get_chip_id() == GP_HIDREV_MAJOR_T210);
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// Set timings for lowpower clocks.
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exec_cfg((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, CFG_SIZE(_di_dsi_timing_deinit_config));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, ARRAY_SIZE(_di_dsi_timing_deinit_config));
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if (_display_id != PANEL_SAM_AMS699VC01)
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usleep(10000);
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@ -739,11 +739,11 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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switch (_display_id)
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{
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case PANEL_JDI_XXX062M:
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, CFG_SIZE(_di_dsi_panel_deinit_config_jdi));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, ARRAY_SIZE(_di_dsi_panel_deinit_config_jdi));
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break;
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case PANEL_AUO_A062TAN01:
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, CFG_SIZE(_di_dsi_panel_deinit_config_auo));
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exec_cfg((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, ARRAY_SIZE(_di_dsi_panel_deinit_config_auo));
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break;
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case PANEL_INL_2J055IA_27A:
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@ -848,7 +848,7 @@ void display_set_decoded_panel_id(u32 id)
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void display_color_screen(u32 color)
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{
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_one_color, CFG_SIZE(_di_win_one_color));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_one_color, ARRAY_SIZE(_di_win_one_color));
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// Configure display to show single color.
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DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
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@ -870,7 +870,7 @@ u32 *display_init_framebuffer_pitch()
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memset((u32 *)IPL_FB_ADDRESS, 0, IPL_FB_SZ);
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// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch, CFG_SIZE(_di_win_framebuffer_pitch));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch, ARRAY_SIZE(_di_win_framebuffer_pitch));
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//usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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@ -881,7 +881,7 @@ u32 *display_init_framebuffer_pitch_vic()
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// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
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if (_display_id != PANEL_SAM_AMS699VC01)
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usleep(8000); // Wait half frame for PWM to apply.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_vic, CFG_SIZE(_di_win_framebuffer_pitch_vic));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_vic, ARRAY_SIZE(_di_win_framebuffer_pitch_vic));
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if (_display_id != PANEL_SAM_AMS699VC01)
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usleep(35000); // Wait 2 frames.
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@ -891,7 +891,7 @@ u32 *display_init_framebuffer_pitch_vic()
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u32 *display_init_framebuffer_pitch_inv()
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{
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// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_inv, CFG_SIZE(_di_win_framebuffer_pitch_inv));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_pitch_inv, ARRAY_SIZE(_di_win_framebuffer_pitch_inv));
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usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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@ -900,7 +900,7 @@ u32 *display_init_framebuffer_pitch_inv()
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u32 *display_init_framebuffer_block()
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{
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// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280.
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_block, CFG_SIZE(_di_win_framebuffer_block));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_block, ARRAY_SIZE(_di_win_framebuffer_block));
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usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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@ -909,7 +909,7 @@ u32 *display_init_framebuffer_block()
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u32 *display_init_framebuffer_log()
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{
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// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_log, CFG_SIZE(_di_win_framebuffer_log));
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exec_cfg((u32 *)DISPLAY_A_BASE, _di_win_framebuffer_log, ARRAY_SIZE(_di_win_framebuffer_log));
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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}
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@ -970,7 +970,7 @@ void display_deactivate_console()
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}
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// Disable window D.
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DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
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DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
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DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0;
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// Arm and activate changes.
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@ -21,8 +21,6 @@
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#include <utils/types.h>
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#include <mem/minerva.h>
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#define CFG_SIZE(array) (sizeof(array) / sizeof(cfg_op_t))
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#define NYX_NEW_INFO 0x3058594E
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typedef enum
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