mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-23 00:22:01 +00:00
Add seconds timer + bugfixes
This commit is contained in:
parent
c215b1c74c
commit
3f18713f53
13 changed files with 54 additions and 45 deletions
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@ -34,7 +34,7 @@ int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
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*value += ((data >> 3) & 1) ? 640 : 0;
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*value += 3880;
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break;
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case BQ24193_IputCurrentLimit: // Input current limit (mA).
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case BQ24193_InputCurrentLimit: // Input current limit (mA).
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data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_InputSource);
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data &= BQ24193_INCONFIG_INLIMIT_MASK;
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switch (data)
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@ -101,7 +101,7 @@ enum BQ24193_reg {
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enum BQ24193_reg_prop {
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BQ24193_InputVoltageLimit, // REG 0.
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BQ24193_IputCurrentLimit, // REG 0.
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BQ24193_InputCurrentLimit, // REG 0.
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BQ24193_SystemMinimumVoltage, // REG 1.
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BQ24193_FastChargeCurrentLimit, // REG 2.
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BQ24193_ChargeVoltageLimit, // REG 4.
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@ -60,14 +60,14 @@ u32 btn_wait()
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u32 btn_wait_timeout(u32 time_ms, u32 mask)
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{
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u32 timeout = get_tmr() + (time_ms * 1000);
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u32 timeout = get_tmr_us() + (time_ms * 1000);
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u32 res = btn_read() & mask;
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do
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{
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if (!(res & mask))
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res = btn_read() & mask;
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} while (get_tmr() < timeout);
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} while (get_tmr_us() < timeout);
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return res;
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}
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@ -106,6 +106,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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/*! Generic clock descriptor. */
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typedef struct _clock_t
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4
ipl/di.c
4
ipl/di.c
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@ -216,8 +216,8 @@ void display_color_screen(u32 color)
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u32 *display_init_framebuffer()
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{
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//Sanitize framebuffer area. Aligned to 4MB.
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memset((u32 *)0xC0000000, 0, 0x400000);
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//Sanitize framebuffer area.
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memset((u32 *)0xC0000000, 0, 0x3C0000);
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//This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);
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@ -127,7 +127,7 @@ void gfx_init_ctxt(gfx_ctxt_t *ctxt, u32 *fb, u32 width, u32 height, u32 stride)
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void gfx_clear_grey(gfx_ctxt_t *ctxt, u8 color)
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{
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memset(ctxt->fb, color, 0x400000);
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memset(ctxt->fb, color, 0x3C0000);
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}
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void gfx_clear_color(gfx_ctxt_t *ctxt, u32 color)
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12
ipl/main.c
12
ipl/main.c
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@ -142,7 +142,7 @@ int sd_save_to_file(void * buf, u32 size, const char * filename)
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{
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FIL fp;
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u32 res = 0;
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res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK;
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res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE);
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if (res) {
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EPRINTFARGS("Error (%d) creating file %s.\n", res, filename);
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return 1;
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@ -880,7 +880,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
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FIL fp;
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gfx_con_getpos(&gfx_con, &gfx_con.savedx, &gfx_con.savedy);
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gfx_printf(&gfx_con, "Filename: %s\n\n", outFilename);
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res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK;
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res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE);
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if (res)
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{
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EPRINTFARGS("Error (%d) creating file %s.\n", res, outFilename);
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@ -972,7 +972,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
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gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
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gfx_printf(&gfx_con, "Filename: %s\n\n", outFilename);
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lbaStartPart = lba_curr;
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res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK;
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res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE);
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if (res)
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{
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EPRINTFARGS("Error (%d) creating file %s.\n", res, outFilename);
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@ -1095,13 +1095,12 @@ static void dump_emmc_selected(dumpType_t dumpType)
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int i = 0;
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char sdPath[64];
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memcpy(sdPath, "Backup/", 7);
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timer = get_tmr();
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// Create Backup/Restore folders, if they do not exist.
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f_mkdir("Backup");
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f_mkdir("Backup/Partitions");
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f_mkdir("Backup/Restore");
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timer = get_tmr_s();
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if (dumpType & DUMP_BOOT)
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{
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static const u32 BOOT_PART_SIZE = 0x400000;
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@ -1175,7 +1174,7 @@ static void dump_emmc_selected(dumpType_t dumpType)
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}
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gfx_putc(&gfx_con, '\n');
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gfx_printf(&gfx_con, "Time taken: %d seconds.\n", (get_tmr() - timer) / 1000000);
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gfx_printf(&gfx_con, "Time taken: %d seconds.\n", get_tmr_s() - timer);
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sdmmc_storage_end(&storage);
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if (res && 0) //TODO: Replace with the config check.
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gfx_printf(&gfx_con, "\n%kFinished and verified!%k\nPress any key...\n",0xFF96FF00, 0xFFCCCCCC);
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@ -1444,7 +1443,6 @@ int fix_attributes(char *path, u32 *total)
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res = fix_attributes(path, total);
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if (res != FR_OK)
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break;
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}
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// Clear file or folder path.
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path[i] = 0;
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12
ipl/sdmmc.c
12
ipl/sdmmc.c
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@ -228,7 +228,7 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
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static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
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{
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u32 timeout = get_tmr() + 1500000;
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u32 timeout = get_tmr_us() + 1500000;
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while (1)
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{
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@ -241,7 +241,7 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
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storage->has_sector_access = 1;
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return 1;
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}
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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break;
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sleep(1000);
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}
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@ -605,7 +605,7 @@ static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, int
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static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, int supports_low_voltage)
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{
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u32 timeout = get_tmr() + 1500000;
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u32 timeout = get_tmr_us() + 1500000;
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while (1)
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{
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@ -633,7 +633,7 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, i
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return 1;
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}
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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break;
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sleep(10000); // Needs to be at least 10ms for some SD Cards
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}
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@ -646,7 +646,7 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage)
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sdmmc_cmd_t cmdbuf;
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sdmmc_init_cmd(&cmdbuf, SD_SEND_RELATIVE_ADDR, 0, SDMMC_RSP_TYPE_4, 0);
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u32 timeout = get_tmr() + 1500000;
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u32 timeout = get_tmr_us() + 1500000;
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while (1)
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{
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@ -663,7 +663,7 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage)
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return 1;
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}
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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break;
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sleep(1000);
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}
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@ -161,20 +161,20 @@ static int _sdmmc_wait_type4(sdmmc_t *sdmmc)
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sdmmc->regs->field_1B0 |= 0x80000000;
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 5000;
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u32 timeout = get_tmr_us() + 5000;
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while (sdmmc->regs->field_1B0 & 0x80000000)
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{
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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res = 0;
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goto out;
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}
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}
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timeout = get_tmr() + 10000;
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timeout = get_tmr_us() + 10000;
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while (sdmmc->regs->field_1BC & 0x80000000)
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{
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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res = 0;
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goto out;
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@ -376,8 +376,8 @@ static void _sdmmc_reset(sdmmc_t *sdmmc)
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sdmmc->regs->swrst |=
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TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE | TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE;
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 2000000;
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while (sdmmc->regs->swrst << 29 >> 30 && get_tmr() < timeout)
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u32 timeout = get_tmr_us() + 2000000;
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while (sdmmc->regs->swrst << 29 >> 30 && get_tmr_us() < timeout)
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;
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}
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@ -385,9 +385,9 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat)
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{
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 2000000;
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u32 timeout = get_tmr_us() + 2000000;
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while(sdmmc->regs->prnsts & 1) //CMD inhibit.
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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_sdmmc_reset(sdmmc);
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return 0;
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@ -395,9 +395,9 @@ static int _sdmmc_wait_prnsts_type0(sdmmc_t *sdmmc, u32 wait_dat)
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if (wait_dat)
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{
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timeout = get_tmr() + 2000000;
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timeout = get_tmr_us() + 2000000;
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while (sdmmc->regs->prnsts & 2) //DAT inhibit.
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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_sdmmc_reset(sdmmc);
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return 0;
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@ -411,9 +411,9 @@ static int _sdmmc_wait_prnsts_type1(sdmmc_t *sdmmc)
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{
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 2000000;
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u32 timeout = get_tmr_us() + 2000000;
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while (!(sdmmc->regs->prnsts & 0x100000)) //DAT0 line level.
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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_sdmmc_reset(sdmmc);
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return 0;
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@ -509,8 +509,8 @@ static int _sdmmc_config_tuning_once(sdmmc_t *sdmmc, u32 cmd)
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 5000;
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while (get_tmr() < timeout)
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u32 timeout = get_tmr_us() + 5000;
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while (get_tmr_us() < timeout)
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{
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if (sdmmc->regs->norintsts & 0x20)
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{
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@ -573,10 +573,10 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
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//Enable internal clock and wait till it is stable.
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sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE;
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 2000000;
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u32 timeout = get_tmr_us() + 2000000;
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while (!(sdmmc->regs->clkcon & TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE))
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{
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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return 0;
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}
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@ -649,10 +649,10 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
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_sdmmc_get_clkcon(sdmmc);
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sleep(1);
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u32 timeout = get_tmr() + 10000;
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u32 timeout = get_tmr_us() + 10000;
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while (sdmmc->regs->autocalcfg & 0x80000000)
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{
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if (get_tmr() > timeout)
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if (get_tmr_us() > timeout)
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{
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//In case autocalibration fails, we load suggested standard values.
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_sdmmc_pad_config_fallback(sdmmc, power);
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@ -710,13 +710,13 @@ static int _sdmmc_wait_request(sdmmc_t *sdmmc)
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{
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_sdmmc_get_clkcon(sdmmc);
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u32 timeout = get_tmr() + 2000000;
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u32 timeout = get_tmr_us() + 2000000;
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while (1)
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{
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int res = _sdmmc_check_mask_interrupt(sdmmc, 0, TEGRA_MMC_NORINTSTS_CMD_COMPLETE);
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if (res == SDMMC_MASKINT_MASKED)
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break;
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if (res != SDMMC_MASKINT_NOERROR || get_tmr() > timeout)
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if (res != SDMMC_MASKINT_NOERROR || get_tmr_us() > timeout)
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{
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_sdmmc_reset(sdmmc);
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return 0;
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@ -817,7 +817,7 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
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do
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{
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blkcnt = sdmmc->regs->blkcnt;
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u32 timeout = get_tmr() + 1500000;
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u32 timeout = get_tmr_us() + 1500000;
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do
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{
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int res = 0;
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@ -843,7 +843,7 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
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_sdmmc_reset(sdmmc);
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return 0;
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}
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} while (get_tmr() < timeout);
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} while (get_tmr_us() < timeout);
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} while (sdmmc->regs->blkcnt != blkcnt);
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_sdmmc_reset(sdmmc);
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@ -43,6 +43,7 @@
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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#define RTC_BASE 0x7000E000
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#define PMC_BASE 0x7000E400
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#define SYSCTR0_BASE 0x7000F000
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#define FUSE_BASE 0x7000F800
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@ -78,6 +79,7 @@
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#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
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#define APB_MISC(off) _REG(APB_MISC_BASE, off)
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#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
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#define RTC(off) _REG(RTC_BASE, off)
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#define PMC(off) _REG(PMC_BASE, off)
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#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
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#define FUSE(off) _REG(FUSE_BASE, off)
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@ -30,6 +30,8 @@ extern u8 *Kc_MENU_LOGO;
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void tui_pbar(gfx_con_t *con, int x, int y, u32 val, u32 fgcol, u32 bgcol)
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{
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u32 cx, cy;
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if (val > 200)
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val = 200;
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gfx_con_getpos(con, &cx, &cy);
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@ -18,9 +18,14 @@
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#include "util.h"
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#include "t210.h"
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u32 get_tmr()
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u32 get_tmr_s()
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{
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return TMR(0x10);
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return RTC(0x8); //APBDEV_RTC_SECONDS
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}
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u32 get_tmr_us()
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{
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return TMR(0x10); //TMRUS
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}
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void sleep(u32 ticks)
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@ -29,7 +29,8 @@ typedef struct _cfg_op_t
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u32 val;
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} cfg_op_t;
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u32 get_tmr();
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u32 get_tmr_us();
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u32 get_tmr_s();
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void sleep(u32 ticks);
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops);
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u32 crc32c(const void *buf, u32 len);
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