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https://github.com/CTCaer/hekate.git
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hwinit: Add T210B01 support
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CTCaer
parent
377825d4fb
commit
795ed8aadc
3 changed files with 89 additions and 51 deletions
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@ -56,6 +56,14 @@ extern volatile nyx_storage_t *nyx_str;
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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u32 hw_get_chip_id()
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{
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if (((APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF) >= GP_HIDREV_MAJOR_T210B01)
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return GP_HIDREV_MAJOR_T210B01;
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else
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return GP_HIDREV_MAJOR_T210;
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}
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static void _config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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@ -79,32 +87,38 @@ static void _config_oscillators()
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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static void _config_gpios()
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static void _config_gpios(bool nx_hoag)
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{
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// Clamp inputs when tristated.
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APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
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PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
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PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
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if (!nx_hoag)
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{
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PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
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PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
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// Set pin mode for UARTB/C TX pins.
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
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#endif
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
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#endif
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// Enable input logic for UARTB/C TX pins.
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gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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}
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// Set Joy-Con IsAttached direction.
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PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
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// Set pin mode for Joy-Con IsAttached and UARTB/C TX pins.
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
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#endif
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
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#endif
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// Set Joy-Con IsAttached mode.
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
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// Enable input logic for Joy-Con IsAttached and UARTB/C TX pins.
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gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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// Enable input logic for Joy-Con IsAttached pins.
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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@ -269,13 +283,13 @@ static void _config_se_brom()
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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static void _config_regulators()
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static void _config_regulators(bool tegra_t210)
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{
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config(false);
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// Disable SDMMC1 IO power.
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
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gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
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max77620_regulator_enable(REGULATOR_LDO2, 0);
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sd_power_cycle_time_start = get_tmr_ms();
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@ -283,46 +297,52 @@ static void _config_regulators()
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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BIT(6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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// Configure all Flexible Power Sequencers.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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max77620_regulator_config_fps(REGULATOR_LDO4);
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max77620_regulator_config_fps(REGULATOR_LDO8);
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max77620_regulator_config_fps(REGULATOR_SD0);
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max77620_regulator_config_fps(REGULATOR_SD1);
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max77620_regulator_config_fps(REGULATOR_SD3);
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if (tegra_t210)
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{
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// Configure all Flexible Power Sequencers for MAX77620.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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max77620_regulator_config_fps(REGULATOR_LDO4);
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max77620_regulator_config_fps(REGULATOR_LDO8);
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max77620_regulator_config_fps(REGULATOR_SD0);
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max77620_regulator_config_fps(REGULATOR_SD1);
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max77620_regulator_config_fps(REGULATOR_SD3);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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// Set vdd_core voltage to 1.125V.
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max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Set vdd_core voltage to 1.125V.
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max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Fix CPU/GPU after a L4T warmboot.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
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// Fix CPU/GPU after a L4T warmboot.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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}
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else // Tegra X1+ set vdd_core voltage to 1.05V.
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max77620_regulator_set_voltage(REGULATOR_SD0, 1050000);
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}
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void hw_init()
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{
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// Get Chip ID.
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG;
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// Bootrom stuff we skipped by going through rcm.
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_config_se_brom();
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//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
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@ -330,7 +350,8 @@ void hw_init()
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PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
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// Perform Memory Built-In Self Test WAR if T210.
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_mbist_workaround();
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if (tegra_t210)
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_mbist_workaround();
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// Enable Security Engine clock.
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clock_enable_se();
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@ -348,7 +369,7 @@ void hw_init()
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_config_oscillators();
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// Initialize pin configuration.
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_config_gpios();
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_config_gpios(nx_hoag);
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#ifdef DEBUG_UART_PORT
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clock_enable_uart(DEBUG_UART_PORT);
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@ -365,21 +386,34 @@ void hw_init()
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// Enable clock to TZRAM.
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clock_enable_tzram();
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// Initialize I2C5, mandatory for PMIC comms.
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i2c_init(I2C_1);
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// Initialize I2C5, mandatory for PMIC.
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i2c_init(I2C_5);
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//! TODO: Why? Device is NFC MCU on Lite.
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if (nx_hoag)
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max77620_regulator_set_volt_and_flags(REGULATOR_LDO8, 2800000, MAX77620_POWER_MODE_NORMAL);
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// Initialize I2C1 for various power related devices.
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i2c_init(I2C_1);
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// Enable charger in case it's disabled.
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bq24193_enable_charger();
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// Initialize various regulators based on Erista/Mariko platform.
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_config_regulators();
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_config_regulators(tegra_t210);
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_config_pmc_scratch(); // Missing from 4.x+
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// Set BPMP/SCLK to PLLP_OUT (408MHz).
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333;
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// Disable TZRAM shutdown control and lock the regs.
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if (!tegra_t210)
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{
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PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= 0xFFFFFFFE;
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PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = 3;
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PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = 3;
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}
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// Initialize External memory controller and configure DRAM parameters.
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sdram_init();
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@ -22,5 +22,6 @@
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void hw_init();
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void hw_reinit_workaround(bool extra_reconfig, u32 magic);
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u32 hw_get_chip_id();
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#endif
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@ -90,6 +90,9 @@
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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int pmc_enable_partition(u32 part, int enable);
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