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https://github.com/CTCaer/hekate.git
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di: restore window config wait for inv pitch and block linear
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parent
aee5861f65
commit
7bb8b1da62
1 changed files with 12 additions and 12 deletions
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@ -311,12 +311,12 @@ void display_init()
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}
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// Enable power to display panel controller.
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// Enable LCD DVDD.
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max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000);
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max7762x_regulator_enable(REGULATOR_LDO0, true);
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if (tegra_t210)
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max77620_config_gpio(7, MAX77620_GPIO_OUTPUT_ENABLE); // T210: LD0 -> GPIO7 -> Display panel.
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max77620_config_gpio(7, MAX77620_GPIO_OUTPUT_ENABLE); // T210: LD0 -> GPIO7 -> LCD.
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// Enable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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@ -352,14 +352,14 @@ void display_init()
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}
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else
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{
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// Set LCD +-5V pins mode and direction
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// Set LCD AVDD pins mode and direction
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gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
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// Enable LCD power.
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // LCD +5V enable.
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// Enable LCD AVDD.
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // LCD AVDD +5.4V enable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // LCD -5V enable.
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // LCD AVDD -5.4V enable.
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usleep(10000);
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// Configure Backlight PWM/EN and LCD RST pins (BL PWM, BL EN, LCD RST).
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@ -697,9 +697,9 @@ skip_panel_deinit:
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if (!nx_aula) // HOS uses panel id.
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{
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD -5V disable.
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD AVDD -5.4V disable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD +5V disable.
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD AVDD +5.4V disable.
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usleep(10000);
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}
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else
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@ -757,7 +757,7 @@ void display_color_screen(u32 color)
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DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
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DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
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DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
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usleep(35000); // No need to wait on Aula.
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usleep(35000); // Wait 2 frames. No need on Aula.
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if (_display_id != PANEL_SAM_AMS699VC01)
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display_backlight(true);
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@ -772,7 +772,7 @@ u32 *display_init_framebuffer_pitch()
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// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
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//usleep(35000); // No need to wait on Aula.
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//usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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}
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@ -781,7 +781,7 @@ u32 *display_init_framebuffer_pitch_inv()
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{
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// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
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//usleep(35000); // No need to wait on Aula.
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usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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}
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@ -790,7 +790,7 @@ u32 *display_init_framebuffer_block()
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{
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// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
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//usleep(35000); // No need to wait on Aula.
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usleep(35000); // Wait 2 frames. No need on Aula.
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return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR));
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}
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