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usb: Split init into PHY init and device init
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parent
721e926a75
commit
8a352bdfe2
1 changed files with 14 additions and 7 deletions
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@ -242,11 +242,8 @@ static void _usb_charger_detect()
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}
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}
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int usb_device_init()
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static void _usb_init_phy()
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{
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if (usb_init_done)
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return 0;
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// Configure and enable PLLU.
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clock_enable_pllu();
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@ -308,7 +305,8 @@ int usb_device_init()
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// Enable crystal clock.
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CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= 0x40000000;
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// Enable USB2 tracking.
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// Enable USB2 tracking clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4.
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@ -331,7 +329,7 @@ int usb_device_init()
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// TRK cycle done. Force PDTRK input into power down.
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USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFF7FFFFF) | 1;
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// Disable USB2_TRK clock and configure UTMIP misc.
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// Disable USB2 tracking clock and configure UTMIP misc.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_CLR) = BIT(CLK_Y_USB2_TRK);
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CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFEFFFFEA) | 0x2000000 | 0x28 | 2;
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usleep(1);
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@ -340,7 +338,7 @@ int usb_device_init()
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usleep(1);
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// Clear power downs on UTMIP ID and VBUS wake up, PD, PD2, PDZI, PDCHRP, PDDR.
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PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up.
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PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up.
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usleep(1);
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USB(USB1_UTMIP_XCVR_CFG0) &= 0xFFFFBFFF; // UTMIP_FORCE_PD_POWERDOWN.
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usleep(1);
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@ -352,6 +350,15 @@ int usb_device_init()
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usleep(1);
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USB(USB1_UTMIP_XCVR_CFG1) &= 0xFFFFFFEF; // UTMIP_FORCE_PDDR_POWERDOWN.
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usleep(1);
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}
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int usb_device_init()
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{
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if (usb_init_done)
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return 0;
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// Initialize USB2 controller PHY.
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_usb_init_phy();
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// AHB USB performance cfg.
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AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_ENB_FAST_REARBITRATE;
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