mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-08 11:31:44 +00:00
Utilize BIT macro everywhere
This commit is contained in:
CTCaer
parent
94486873c1
commit
cabaa6cfb8
43 changed files with 517 additions and 515 deletions
16
bdk/gfx/di.c
16
bdk/gfx/di.c
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -77,9 +77,9 @@ void display_init()
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz).
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// Disable deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
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// Bring every IO rail out of deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
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// Config LCD and Backlight pins.
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN
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@ -255,7 +255,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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display_backlight_brightness(0, 1000);
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DSI(_DSIREG(DSI_WR_DATA)) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE;
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
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@ -324,7 +324,7 @@ skip_panel_deinit:
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode.
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}
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void display_end() { _display_panel_and_hw_end(false); };
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@ -386,7 +386,7 @@ u32 *display_init_framebuffer_log()
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void display_activate_console()
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{
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
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DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
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DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
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DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
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@ -407,7 +407,7 @@ void display_activate_console()
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void display_deactivate_console()
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{
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
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DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D.
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for (u32 i = 0xFFFF; i > 0xFF7F; i--)
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{
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147
bdk/gfx/di.h
147
bdk/gfx/di.h
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -42,11 +42,11 @@
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#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
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#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
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#define SYNCPT_CNTRL_NO_STALL (1 << 8)
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#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
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#define SYNCPT_CNTRL_SOFT_RESET BIT(0)
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#define SYNCPT_CNTRL_NO_STALL BIT(8)
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#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
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#define SYNCPT_VSYNC_ENABLE (1 << 8)
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#define SYNCPT_VSYNC_ENABLE BIT(8)
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#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
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@ -57,42 +57,42 @@
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#define DISP_CTRL_MODE_MASK (3 << 5)
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#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
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#define PW0_ENABLE (1 << 0)
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#define PW1_ENABLE (1 << 2)
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#define PW2_ENABLE (1 << 4)
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#define PW3_ENABLE (1 << 6)
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#define PW4_ENABLE (1 << 8)
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#define PM0_ENABLE (1 << 16)
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#define PM1_ENABLE (1 << 18)
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#define PW0_ENABLE BIT(0)
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#define PW1_ENABLE BIT(2)
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#define PW2_ENABLE BIT(4)
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#define PW3_ENABLE BIT(6)
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#define PW4_ENABLE BIT(8)
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#define PM0_ENABLE BIT(16)
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#define PM1_ENABLE BIT(18)
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_ENABLE 0x39
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#define DC_CMD_STATE_ACCESS 0x40
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#define READ_MUX (1 << 0)
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#define WRITE_MUX (1 << 2)
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#define READ_MUX BIT(0)
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#define WRITE_MUX BIT(2)
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#define DC_CMD_STATE_CONTROL 0x41
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#define GENERAL_ACT_REQ (1 << 0)
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#define WIN_A_ACT_REQ (1 << 1)
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#define WIN_B_ACT_REQ (1 << 2)
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#define WIN_C_ACT_REQ (1 << 3)
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#define WIN_D_ACT_REQ (1 << 4)
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#define CURSOR_ACT_REQ (1 << 7)
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#define GENERAL_UPDATE (1 << 8)
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#define WIN_A_UPDATE (1 << 9)
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#define WIN_B_UPDATE (1 << 10)
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#define WIN_C_UPDATE (1 << 11)
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#define WIN_D_UPDATE (1 << 12)
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#define CURSOR_UPDATE (1 << 15)
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#define NC_HOST_TRIG (1 << 24)
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#define GENERAL_ACT_REQ BIT(0)
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#define WIN_A_ACT_REQ BIT(1)
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#define WIN_B_ACT_REQ BIT(2)
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#define WIN_C_ACT_REQ BIT(3)
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#define WIN_D_ACT_REQ BIT(4)
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#define CURSOR_ACT_REQ BIT(7)
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#define GENERAL_UPDATE BIT(8)
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#define WIN_A_UPDATE BIT(9)
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#define WIN_B_UPDATE BIT(10)
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#define WIN_C_UPDATE BIT(11)
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#define WIN_D_UPDATE BIT(12)
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#define CURSOR_UPDATE BIT(15)
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#define NC_HOST_TRIG BIT(24)
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#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
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#define WINDOW_A_SELECT (1 << 4)
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#define WINDOW_B_SELECT (1 << 5)
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#define WINDOW_C_SELECT (1 << 6)
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#define WINDOW_D_SELECT (1 << 7)
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#define WINDOW_A_SELECT BIT(4)
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#define WINDOW_B_SELECT BIT(5)
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#define WINDOW_C_SELECT BIT(6)
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#define WINDOW_D_SELECT BIT(7)
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#define DC_CMD_REG_ACT_CONTROL 0x043
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@ -125,12 +125,13 @@
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// DC_DISP shadowed registers.
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DSI_ENABLE (1 << 29)
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#define SOR1_TIMING_CYA (1 << 27)
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#define SOR1_ENABLE (1 << 26)
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#define SOR_ENABLE (1 << 25)
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#define CURSOR_ENABLE (1 << 16)
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#define CURSOR_ENABLE BIT(16)
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#define SOR_ENABLE BIT(25)
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#define SOR1_ENABLE BIT(26)
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#define SOR1_TIMING_CYA BIT(27)
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#define DSI_ENABLE BIT(29)
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#define HDMI_ENABLE BIT(30)
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
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@ -142,6 +143,7 @@
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#define DC_DISP_FRONT_PORCH 0x40A
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#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
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#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
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#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
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@ -155,7 +157,6 @@
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#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
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#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
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#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
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#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
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@ -189,8 +190,8 @@
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#define BASE_COLOR_SIZE_888 (8 << 0)
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#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
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#define SC1_H_QUALIFIER_NONE (1 << 16)
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#define SC0_H_QUALIFIER_NONE (1 << 0)
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#define SC0_H_QUALIFIER_NONE BIT(0)
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#define SC1_H_QUALIFIER_NONE BIT(16)
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#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
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#define DE_SELECT_ACTIVE_BLANK (0 << 0)
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@ -217,6 +218,7 @@
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#define CURSOR_SIZE_128 (2 << 24)
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#define CURSOR_SIZE_256 (3 << 24)
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#define DC_DISP_CURSOR_POSITION 0x440
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#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
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#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
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#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
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#define CURSOR_BLEND_2BIT (0 << 24)
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@ -247,12 +249,12 @@
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// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
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#define DC_WIN_WIN_OPTIONS 0x700
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#define H_DIRECTION (1 << 0)
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#define V_DIRECTION (1 << 2)
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#define SCAN_COLUMN (1 << 4)
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#define COLOR_EXPAND (1 << 6)
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#define CSC_ENABLE (1 << 18)
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#define WIN_ENABLE (1 << 30)
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#define H_DIRECTION BIT(0)
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#define V_DIRECTION BIT(2)
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#define SCAN_COLUMN BIT(4)
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#define COLOR_EXPAND BIT(6)
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#define CSC_ENABLE BIT(18)
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#define WIN_ENABLE BIT(30)
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#define DC_WIN_BUFFER_CONTROL 0x702
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#define BUFFER_CONTROL_HOST 0
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@ -369,36 +371,36 @@
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#define DSI_INT_MASK 0xE
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#define DSI_HOST_CONTROL 0xF
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#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
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#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
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#define DSI_HOST_CONTROL_ECC BIT(0)
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#define DSI_HOST_CONTROL_CS BIT(1)
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#define DSI_HOST_CONTROL_PKT_BTA BIT(2)
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#define DSI_HOST_CONTROL_IMM_BTA BIT(3)
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#define DSI_HOST_CONTROL_FIFO_SEL BIT(4)
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#define DSI_HOST_CONTROL_HS BIT(5)
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#define DSI_HOST_CONTROL_RAW BIT(6)
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#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
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#define DSI_HOST_CONTROL_RAW (1 << 6)
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#define DSI_HOST_CONTROL_HS (1 << 5)
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#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
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#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
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#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
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#define DSI_HOST_CONTROL_CS (1 << 1)
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#define DSI_HOST_CONTROL_ECC (1 << 0)
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#define DSI_HOST_CONTROL_CRC_RESET BIT(20)
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#define DSI_HOST_CONTROL_FIFO_RESET BIT(21)
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#define DSI_CONTROL 0x10
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#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
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#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
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#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
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#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
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#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
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#define DSI_CONTROL_DCS_ENABLE (1 << 3)
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#define DSI_CONTROL_HOST_ENABLE BIT(0)
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#define DSI_CONTROL_VIDEO_ENABLE BIT(1)
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#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
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#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
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#define DSI_CONTROL_HOST_ENABLE (1 << 0)
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#define DSI_CONTROL_DCS_ENABLE BIT(3)
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#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
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#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
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#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
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#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
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#define DSI_CONTROL_HS_CLK_CTRL BIT(20)
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#define DSI_SOL_DELAY 0x11
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#define DSI_MAX_THRESHOLD 0x12
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#define DSI_TRIGGER 0x13
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#define DSI_TRIGGER_HOST (1 << 1)
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#define DSI_TRIGGER_VIDEO (1 << 0)
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#define DSI_TRIGGER_VIDEO BIT(0)
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#define DSI_TRIGGER_HOST BIT(1)
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#define DSI_TX_CRC 0x14
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#define DSI_STATUS 0x15
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@ -430,20 +432,20 @@
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#define DSI_BTA_TIMING 0x3F
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#define DSI_TIMEOUT_0 0x44
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#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
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#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_1 0x45
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#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
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#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
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#define DSI_TO_TALLY 0x46
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#define DSI_PAD_CONTROL_0 0x4B
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#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
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#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK BIT(8)
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#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
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#define DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24)
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#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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@ -453,10 +455,10 @@
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#define DSI_PAD_CONTROL_2 0x50
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#define DSI_PAD_CONTROL_3 0x51
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#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
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#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
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#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
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#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
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#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
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#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
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#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
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#define DSI_PAD_CONTROL_4 0x52
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#define DSI_INIT_SEQ_DATA_15 0x5F
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@ -493,6 +495,7 @@
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#define MIPI_DCS_GET_DISPLAY_ID 0x04
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#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
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#define MIPI_DCS_EXIT_SLEEP_MODE 0x11
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#define MIPI_DCS_SET_DISPLAY_OFF 0x28
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#define MIPI_DCS_SET_DISPLAY_ON 0x29
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/* Switch Panels:
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@ -45,8 +45,8 @@
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#define BH1730_DATA1LOW_REG 0x16
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#define BH1730_DATA1HIGH_REG 0x17
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#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | reg)
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#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | cmd)
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#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | (reg))
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#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | (cmd))
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typedef struct _als_table_t
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{
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@ -232,7 +232,7 @@
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#define EMC_COMP_PAD_SW_CTRL 0x57c
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#define EMC_REQ_CTRL 0x2b0
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||||
#define EMC_EMC_STATUS 0x2b4
|
||||
#define EMC_STATUS_MRR_DIVLD (1 << 20)
|
||||
#define EMC_STATUS_MRR_DIVLD BIT(20)
|
||||
#define EMC_CFG_2 0x2b8
|
||||
#define EMC_CFG_DIG_DLL 0x2bc
|
||||
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
|
||||
|
|
|
|||
|
|
@ -503,14 +503,14 @@
|
|||
#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L2 (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
|
||||
#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L3 (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT)
|
||||
|
||||
#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU (1 << 22)
|
||||
#define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU BIT(22)
|
||||
|
||||
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK (1 << 23)
|
||||
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK (1 << 24)
|
||||
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_WR_EN_BYPASS_CHECK BIT(23)
|
||||
#define SEC_CARVEOUT_CFG_TZ_GLOBAL_RD_EN_BYPASS_CHECK BIT(24)
|
||||
|
||||
#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH (1 << 25)
|
||||
#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH (1 << 26)
|
||||
#define SEC_CARVEOUT_CFG_ALLOW_APERTURE_ID_MISMATCH BIT(25)
|
||||
#define SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH BIT(26)
|
||||
|
||||
#define SEC_CARVEOUT_CFG_IS_WPR (1 << 27)
|
||||
#define SEC_CARVEOUT_CFG_IS_WPR BIT(27)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -86,13 +86,18 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
|
|||
{
|
||||
emc_mr_data_t data;
|
||||
|
||||
// Device 0.
|
||||
_sdram_req_mrr_data((1 << 31) | (mrx << 16), EMC_CHAN0);
|
||||
/*
|
||||
* When a dram chip has only one rank, then the info from the 2 ranks differs.
|
||||
* Info not matching is only allowed on different channels.
|
||||
*/
|
||||
|
||||
// Get Device 0 (Rank 0) info from both dram chips (channels).
|
||||
_sdram_req_mrr_data(BIT(31) | (mrx << 16), EMC_CHAN0);
|
||||
data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
|
||||
data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
|
||||
|
||||
// Device 1.
|
||||
_sdram_req_mrr_data((1 << 30) | (mrx << 16), EMC_CHAN1);
|
||||
// Get Device 1 (Rank 1) info from both dram chips (channels).
|
||||
_sdram_req_mrr_data(BIT(30) | (mrx << 16), EMC_CHAN1);
|
||||
data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
|
||||
data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
|
||||
|
||||
|
|
@ -545,7 +550,7 @@ break_nosleep:
|
|||
EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
|
||||
|
||||
// Patch BootROM.
|
||||
if (params->boot_rom_patch_control & (1 << 31))
|
||||
if (params->boot_rom_patch_control & BIT(31))
|
||||
{
|
||||
*(vu32 *)(APB_MISC_BASE + params->boot_rom_patch_control * 4) = params->boot_rom_patch_data;
|
||||
MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update.
|
||||
|
|
@ -765,7 +770,7 @@ sdram_params_t *sdram_get_params_patched()
|
|||
sdram_params_t *sdram_params = sdram_get_params();
|
||||
|
||||
// Disable Warmboot signature check.
|
||||
sdram_params->boot_rom_patch_control = (1 << 31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
|
||||
sdram_params->boot_rom_patch_control = BIT(31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
|
||||
sdram_params->boot_rom_patch_data = IPATCH_CONFIG(0x10459E, 0x2000);
|
||||
/*
|
||||
// Disable SBK lock.
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
#define DRAM_CFG_SIZE 1896
|
||||
|
||||
#define DRAM_ID(x) (1 << (x))
|
||||
#define DRAM_ID(x) BIT(x)
|
||||
|
||||
#define DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH 0
|
||||
#define DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN 1
|
||||
|
|
|
|||
|
|
@ -27,16 +27,16 @@
|
|||
#include <utils/util.h>
|
||||
|
||||
/* Status register bits */
|
||||
#define STATUS_POR_BIT (1 << 1)
|
||||
#define STATUS_BST_BIT (1 << 3)
|
||||
#define STATUS_VMN_BIT (1 << 8)
|
||||
#define STATUS_TMN_BIT (1 << 9)
|
||||
#define STATUS_SMN_BIT (1 << 10)
|
||||
#define STATUS_BI_BIT (1 << 11)
|
||||
#define STATUS_VMX_BIT (1 << 12)
|
||||
#define STATUS_TMX_BIT (1 << 13)
|
||||
#define STATUS_SMX_BIT (1 << 14)
|
||||
#define STATUS_BR_BIT (1 << 15)
|
||||
#define STATUS_POR_BIT BIT(1)
|
||||
#define STATUS_BST_BIT BIT(3)
|
||||
#define STATUS_VMN_BIT BIT(8)
|
||||
#define STATUS_TMN_BIT BIT(9)
|
||||
#define STATUS_SMN_BIT BIT(10)
|
||||
#define STATUS_BI_BIT BIT(11)
|
||||
#define STATUS_VMX_BIT BIT(12)
|
||||
#define STATUS_TMX_BIT BIT(13)
|
||||
#define STATUS_SMX_BIT BIT(14)
|
||||
#define STATUS_BR_BIT BIT(15)
|
||||
|
||||
#define VFSOC0_LOCK 0x0000
|
||||
#define VFSOC0_UNLOCK 0x0080
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
/*
|
||||
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||
* Note that Maxim 8966 and 8997 are mfd and this is its subdevice.
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics
|
||||
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||
|
|
@ -26,7 +25,7 @@
|
|||
|
||||
#include <utils/types.h>
|
||||
|
||||
#define MAX17050_STATUS_BattAbsent (1 << 3)
|
||||
#define MAX17050_STATUS_BattAbsent BIT(3)
|
||||
#define MAX17050_DEFAULT_SNS_RESISTOR 10000
|
||||
|
||||
/* Consider RepCap which is less then 10 units below FullCAP full */
|
||||
|
|
|
|||
|
|
@ -16,13 +16,7 @@
|
|||
|
||||
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
|
||||
#define MAX77620_REG_CNFGGLBL1 0x00
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7)
|
||||
#define MAX77620_CNFGGLBL1_MPPLD (1 << 6)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4))
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_100 (0 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_MASK 0x0E
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_2700 (0 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_2800 (1 << 1)
|
||||
|
|
@ -32,14 +26,20 @@
|
|||
#define MAX77620_CNFGGLBL1_LBDAC_3200 (5 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3300 (6 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3400 (7 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_100 (0 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
|
||||
#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
|
||||
|
||||
#define MAX77620_REG_CNFGGLBL2 0x01
|
||||
#define MAX77620_REG_CNFGGLBL3 0x02
|
||||
#define MAX77620_WDTC_MASK 0x3
|
||||
#define MAX77620_WDTOFFC (1 << 4)
|
||||
#define MAX77620_WDTSLPC (1 << 3)
|
||||
#define MAX77620_WDTEN (1 << 2)
|
||||
#define MAX77620_WDTEN BIT(2)
|
||||
#define MAX77620_WDTSLPC BIT(3)
|
||||
#define MAX77620_WDTOFFC BIT(4)
|
||||
#define MAX77620_TWD_MASK 0x3
|
||||
#define MAX77620_TWD_2s 0x0
|
||||
#define MAX77620_TWD_16s 0x1
|
||||
|
|
@ -47,15 +47,15 @@
|
|||
#define MAX77620_TWD_128s 0x3
|
||||
|
||||
#define MAX77620_REG_CNFG1_32K 0x03
|
||||
#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2)
|
||||
#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
|
||||
|
||||
#define MAX77620_REG_CNFGBBC 0x04
|
||||
#define MAX77620_CNFGBBC_ENABLE (1 << 0)
|
||||
#define MAX77620_CNFGBBC_ENABLE BIT(0)
|
||||
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
|
||||
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
|
||||
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
|
||||
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
|
||||
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
|
||||
#define MAX77620_CNFGBBC_RESISTOR_100 (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
|
|
@ -64,19 +64,19 @@
|
|||
#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
|
||||
#define MAX77620_REG_IRQTOP 0x05
|
||||
#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7)
|
||||
#define MAX77620_IRQ_TOP_SD_MASK (1 << 6)
|
||||
#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5)
|
||||
#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4)
|
||||
#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3)
|
||||
#define MAX77620_IRQ_TOP_32K_MASK (1 << 2)
|
||||
#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1)
|
||||
#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
|
||||
#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
|
||||
#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
|
||||
#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
|
||||
#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
|
||||
#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
|
||||
#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
|
||||
|
||||
#define MAX77620_REG_INTLBT 0x06
|
||||
#define MAX77620_REG_IRQTOPM 0x0D
|
||||
#define MAX77620_IRQ_LBM_MASK (1 << 3)
|
||||
#define MAX77620_IRQ_TJALRM1_MASK (1 << 2)
|
||||
#define MAX77620_IRQ_TJALRM2_MASK (1 << 1)
|
||||
#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
|
||||
#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
|
||||
#define MAX77620_IRQ_LBM_MASK BIT(3)
|
||||
|
||||
#define MAX77620_REG_IRQSD 0x07
|
||||
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
|
||||
|
|
@ -86,7 +86,7 @@
|
|||
#define MAX77620_REG_NVERC 0x0C
|
||||
|
||||
#define MAX77620_REG_INTENLBT 0x0E
|
||||
#define MAX77620_GLBLM_MASK (1 << 0)
|
||||
#define MAX77620_GLBLM_MASK BIT(0)
|
||||
|
||||
#define MAX77620_REG_IRQMASKSD 0x0F
|
||||
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
|
||||
|
|
@ -132,23 +132,23 @@
|
|||
#define MAX77620_REG_LDO7_CFG2 0x32
|
||||
#define MAX77620_REG_LDO8_CFG 0x33
|
||||
#define MAX77620_REG_LDO8_CFG2 0x34
|
||||
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_SLOW 0
|
||||
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
|
||||
#define MAX20024_LDO_CFG2_MPOK_MASK BIT(2)
|
||||
#define MAX77620_LDO_POWER_MODE_MASK 0xC0
|
||||
#define MAX77620_LDO_POWER_MODE_SHIFT 6
|
||||
#define MAX77620_POWER_MODE_NORMAL 3
|
||||
#define MAX77620_POWER_MODE_LPM 2
|
||||
#define MAX77620_POWER_MODE_GLPM 1
|
||||
#define MAX77620_POWER_MODE_DISABLE 0
|
||||
#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2)
|
||||
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_SLOW 0
|
||||
|
||||
#define MAX77620_REG_LDO_CFG3 0x35
|
||||
#define MAX77620_TRACK4_MASK (1 << 5)
|
||||
#define MAX77620_TRACK4_SHIFT 5
|
||||
#define MAX77620_TRACK4_MASK (1 << MAX77620_TRACK4_SHIFT)
|
||||
|
||||
#define MAX77620_LDO_SLEW_RATE_MASK 0x1
|
||||
|
||||
|
|
@ -183,19 +183,19 @@
|
|||
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
|
||||
|
||||
#define MAX77620_REG_ONOFFCNFG1 0x41
|
||||
#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7)
|
||||
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
|
||||
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
|
||||
#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2)
|
||||
#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1)
|
||||
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
|
||||
#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
|
||||
#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
|
||||
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
|
||||
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
|
||||
#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
|
||||
|
||||
#define MAX77620_REG_ONOFFCNFG2 0x42
|
||||
#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7)
|
||||
#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6)
|
||||
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5)
|
||||
#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2)
|
||||
#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0)
|
||||
#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
|
||||
#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
|
||||
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
|
||||
#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
|
||||
#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
|
||||
|
||||
/* FPS Registers */
|
||||
#define MAX77620_REG_FPS_CFG0 0x43
|
||||
|
|
@ -259,8 +259,8 @@
|
|||
#define MAX77620_CID_DIDM_SHIFT 4
|
||||
|
||||
/* CNCG2SD */
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
|
||||
|
||||
/* Device Identification Metal */
|
||||
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
|
||||
|
|
@ -272,29 +272,29 @@
|
|||
#define MAX77620_SD_SR_SHIFT 6
|
||||
#define MAX77620_SD_POWER_MODE_MASK 0x30
|
||||
#define MAX77620_SD_POWER_MODE_SHIFT 4
|
||||
#define MAX77620_SD_CFG1_ADE_MASK (1 << 3)
|
||||
#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
|
||||
#define MAX77620_SD_CFG1_ADE_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3)
|
||||
#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
|
||||
#define MAX77620_SD_FPWM_MASK 0x04
|
||||
#define MAX77620_SD_FPWM_SHIFT 2
|
||||
#define MAX77620_SD_FSRADE_MASK 0x01
|
||||
#define MAX77620_SD_FSRADE_SHIFT 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2)
|
||||
#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
|
||||
#define MAX20024_SD_CFG1_MPOK_MASK BIT(1)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
|
||||
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
|
||||
|
||||
/* Interrupts */
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@
|
|||
#define MAX77621_CONTROL2_REG 3
|
||||
|
||||
/* MAX77621_VOUT */
|
||||
#define MAX77621_VOUT_ENABLE (1 << 7)
|
||||
#define MAX77621_VOUT_ENABLE BIT(7)
|
||||
#define MAX77621_VOUT_MASK 0x7F
|
||||
#define MAX77621_VOUT_0_95V 0x37
|
||||
#define MAX77621_VOUT_1_09V 0x4F
|
||||
|
|
@ -78,12 +78,12 @@
|
|||
#define MAX77621_DVS_VOUT_MASK 0x7F
|
||||
|
||||
/* MAX77621_CONTROL1 */
|
||||
#define MAX77621_SNS_ENABLE (1 << 7)
|
||||
#define MAX77621_FPWM_EN_M (1 << 6)
|
||||
#define MAX77621_NFSR_ENABLE (1 << 5)
|
||||
#define MAX77621_AD_ENABLE (1 << 4)
|
||||
#define MAX77621_BIAS_ENABLE (1 << 3)
|
||||
#define MAX77621_FREQSHIFT_9PER (1 << 2)
|
||||
#define MAX77621_FREQSHIFT_9PER BIT(2)
|
||||
#define MAX77621_BIAS_ENABLE BIT(3)
|
||||
#define MAX77621_AD_ENABLE BIT(4)
|
||||
#define MAX77621_NFSR_ENABLE BIT(5)
|
||||
#define MAX77621_FPWM_EN_M BIT(6)
|
||||
#define MAX77621_SNS_ENABLE BIT(7)
|
||||
|
||||
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||
|
|
@ -92,10 +92,10 @@
|
|||
#define MAX77621_RAMP_MASK 0x3
|
||||
|
||||
/* MAX77621_CONTROL2 */
|
||||
#define MAX77621_WDTMR_ENABLE (1 << 6)
|
||||
#define MAX77621_DISCH_ENBABLE (1 << 5)
|
||||
#define MAX77621_FT_ENABLE (1 << 4)
|
||||
#define MAX77621_T_JUNCTION_120 (1 << 7)
|
||||
#define MAX77621_FT_ENABLE BIT(4)
|
||||
#define MAX77621_DISCH_ENBABLE BIT(5)
|
||||
#define MAX77621_WDTMR_ENABLE BIT(6)
|
||||
#define MAX77621_T_JUNCTION_120 BIT(7)
|
||||
|
||||
#define MAX77621_CKKADV_TRIP_DISABLE 0xC
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
|
||||
enum
|
||||
{
|
||||
REGULATOR_5V_FAN = (1 << 0),
|
||||
REGULATOR_5V_JC_R = (1 << 1),
|
||||
REGULATOR_5V_JC_L = (1 << 2),
|
||||
REGULATOR_5V_FAN = BIT(0),
|
||||
REGULATOR_5V_JC_R = BIT(1),
|
||||
REGULATOR_5V_JC_L = BIT(2),
|
||||
REGULATOR_5V_ALL = 0xFF
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -27,17 +27,17 @@
|
|||
|
||||
#define MAX77620_RTC_CONTROLM_REG 0x02
|
||||
#define MAX77620_RTC_CONTROL_REG 0x03
|
||||
#define MAX77620_RTC_BIN_FORMAT (1 << 0)
|
||||
#define MAX77620_RTC_24H (1 << 1)
|
||||
#define MAX77620_RTC_BIN_FORMAT BIT(0)
|
||||
#define MAX77620_RTC_24H BIT(1)
|
||||
|
||||
#define MAX77620_RTC_UPDATE0_REG 0x04
|
||||
#define MAX77620_RTC_WRITE_UPDATE (1 << 0)
|
||||
#define MAX77620_RTC_READ_UPDATE (1 << 4)
|
||||
#define MAX77620_RTC_WRITE_UPDATE BIT(0)
|
||||
#define MAX77620_RTC_READ_UPDATE BIT(4)
|
||||
|
||||
#define MAX77620_RTC_SEC_REG 0x07
|
||||
#define MAX77620_RTC_MIN_REG 0x08
|
||||
#define MAX77620_RTC_HOUR_REG 0x09
|
||||
#define MAX77620_RTC_HOUR_PM_MASK (1 << 6)
|
||||
#define MAX77620_RTC_HOUR_PM_MASK BIT(6)
|
||||
#define MAX77620_RTC_WEEKDAY_REG 0x0A
|
||||
#define MAX77620_RTC_MONTH_REG 0x0B
|
||||
#define MAX77620_RTC_YEAR_REG 0x0C
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
#define MAX77620_ALARM2_MONTH_REG 0x19
|
||||
#define MAX77620_ALARM2_YEAR_REG 0x1A
|
||||
#define MAX77620_ALARM2_DATE_REG 0x1B
|
||||
#define MAX77620_RTC_ALARM_EN_MASK (1 << 7)
|
||||
#define MAX77620_RTC_ALARM_EN_MASK BIT(7)
|
||||
|
||||
typedef struct _rtc_time_t {
|
||||
u8 weekday;
|
||||
|
|
|
|||
|
|
@ -172,7 +172,7 @@ void se_rsa_acc_ctrl(u32 rs, u32 flags)
|
|||
((flags >> SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |
|
||||
((flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG) ^ SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG);
|
||||
if (flags & SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG)
|
||||
SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) &= ~(1 << rs);
|
||||
SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) &= ~BIT(rs);
|
||||
}
|
||||
|
||||
void se_key_acc_ctrl(u32 ks, u32 flags)
|
||||
|
|
@ -180,7 +180,7 @@ void se_key_acc_ctrl(u32 ks, u32 flags)
|
|||
if (flags & SE_KEY_TBL_DIS_KEY_ACCESS_FLAG)
|
||||
SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks) = ~flags;
|
||||
if (flags & SE_KEY_TBL_DIS_KEY_LOCK_FLAG)
|
||||
SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) &= ~(1 << ks);
|
||||
SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) &= ~BIT(ks);
|
||||
}
|
||||
|
||||
u32 se_key_acc_ctrl_get(u32 ks)
|
||||
|
|
|
|||
|
|
@ -277,13 +277,13 @@
|
|||
#define SE_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
|
||||
|
||||
#define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284
|
||||
#define SE_KEY_TBL_DIS_KEYREAD_FLAG (1 << 0)
|
||||
#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG (1 << 1)
|
||||
#define SE_KEY_TBL_DIS_OIVREAD_FLAG (1 << 2)
|
||||
#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG (1 << 3)
|
||||
#define SE_KEY_TBL_DIS_UIVREAD_FLAG (1 << 4)
|
||||
#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG (1 << 5)
|
||||
#define SE_KEY_TBL_DIS_KEYUSE_FLAG (1 << 6)
|
||||
#define SE_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_KEY_TBL_DIS_OIVREAD_FLAG BIT(2)
|
||||
#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG BIT(3)
|
||||
#define SE_KEY_TBL_DIS_UIVREAD_FLAG BIT(4)
|
||||
#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG BIT(5)
|
||||
#define SE_KEY_TBL_DIS_KEYUSE_FLAG BIT(6)
|
||||
#define SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
|
||||
|
||||
#define SE_KEY_READ_DISABLE_SHIFT 0
|
||||
|
|
@ -340,11 +340,11 @@
|
|||
#define SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
|
||||
|
||||
#define SE_RSA_KEYTABLE_ACCESS_REG_OFFSET 0x410
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG (1 << 0)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG (1 << 1)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG (1 << 2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT (1 << 2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG BIT(2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT BIT(2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG 7
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG 0x7F
|
||||
|
||||
|
|
|
|||
|
|
@ -20,30 +20,30 @@
|
|||
#define TSEC_BOOTKEYVER 0x1040
|
||||
#define TSEC_STATUS 0x1044
|
||||
#define TSEC_ITFEN 0x1048
|
||||
#define TSEC_ITFEN_CTXEN (1 << 0)
|
||||
#define TSEC_ITFEN_MTHDEN (1 << 1)
|
||||
#define TSEC_ITFEN_CTXEN BIT(0)
|
||||
#define TSEC_ITFEN_MTHDEN BIT(1)
|
||||
#define TSEC_IRQMSET 0x1010
|
||||
#define TSEC_IRQMSET_WDTMR (1 << 1)
|
||||
#define TSEC_IRQMSET_HALT (1 << 4)
|
||||
#define TSEC_IRQMSET_EXTERR (1 << 5)
|
||||
#define TSEC_IRQMSET_SWGEN0 (1 << 6)
|
||||
#define TSEC_IRQMSET_SWGEN1 (1 << 7)
|
||||
#define TSEC_IRQMSET_WDTMR BIT(1)
|
||||
#define TSEC_IRQMSET_HALT BIT(4)
|
||||
#define TSEC_IRQMSET_EXTERR BIT(5)
|
||||
#define TSEC_IRQMSET_SWGEN0 BIT(6)
|
||||
#define TSEC_IRQMSET_SWGEN1 BIT(7)
|
||||
#define TSEC_IRQMSET_EXT(val) (((val) & 0xFF) << 8)
|
||||
#define TSEC_IRQDEST 0x101C
|
||||
#define TSEC_IRQDEST_HALT (1 << 4)
|
||||
#define TSEC_IRQDEST_EXTERR (1 << 5)
|
||||
#define TSEC_IRQDEST_SWGEN0 (1 << 6)
|
||||
#define TSEC_IRQDEST_SWGEN1 (1 << 7)
|
||||
#define TSEC_IRQDEST_HALT BIT(4)
|
||||
#define TSEC_IRQDEST_EXTERR BIT(5)
|
||||
#define TSEC_IRQDEST_SWGEN0 BIT(6)
|
||||
#define TSEC_IRQDEST_SWGEN1 BIT(7)
|
||||
#define TSEC_IRQDEST_EXT(val) (((val) & 0xFF) << 8)
|
||||
#define TSEC_CPUCTL 0x1100
|
||||
#define TSEC_CPUCTL_STARTCPU (1 << 1)
|
||||
#define TSEC_CPUCTL_STARTCPU BIT(1)
|
||||
#define TSEC_BOOTVEC 0x1104
|
||||
#define TSEC_DMACTL 0x110C
|
||||
#define TSEC_DMATRFBASE 0x1110
|
||||
#define TSEC_DMATRFMOFFS 0x1114
|
||||
#define TSEC_DMATRFCMD 0x1118
|
||||
#define TSEC_DMATRFCMD_IDLE (1 << 1)
|
||||
#define TSEC_DMATRFCMD_IMEM (1 << 4)
|
||||
#define TSEC_DMATRFCMD_IDLE BIT(1)
|
||||
#define TSEC_DMATRFCMD_IMEM BIT(4)
|
||||
#define TSEC_DMATRFCMD_SIZE_256B (6 << 8)
|
||||
#define TSEC_DMATRFFBOFFS 0x111C
|
||||
|
||||
|
|
|
|||
|
|
@ -25,38 +25,38 @@
|
|||
#define BPMP_MMU_CACHE_LINE_SIZE 0x20
|
||||
|
||||
#define BPMP_CACHE_CONFIG 0x0
|
||||
#define CFG_ENABLE_CACHE (1 << 0)
|
||||
#define CFG_ENABLE_SKEW_ASSOC (1 << 1)
|
||||
#define CFG_DISABLE_RANDOM_ALLOC (1 << 2)
|
||||
#define CFG_FORCE_WRITE_THROUGH (1 << 3)
|
||||
#define CFG_NEVER_ALLOCATE (1 << 6)
|
||||
#define CFG_ENABLE_INTERRUPT (1 << 7)
|
||||
#define CFG_ENABLE_CACHE BIT(0)
|
||||
#define CFG_ENABLE_SKEW_ASSOC BIT(1)
|
||||
#define CFG_DISABLE_RANDOM_ALLOC BIT(2)
|
||||
#define CFG_FORCE_WRITE_THROUGH BIT(3)
|
||||
#define CFG_NEVER_ALLOCATE BIT(6)
|
||||
#define CFG_ENABLE_INTERRUPT BIT(7)
|
||||
#define CFG_MMU_TAG_MODE(x) ((x) << 8)
|
||||
#define TAG_MODE_PARALLEL 0
|
||||
#define TAG_MODE_TAG_FIRST 1
|
||||
#define TAG_MODE_MMU_FIRST 2
|
||||
#define CFG_DISABLE_WRITE_BUFFER (1 << 10)
|
||||
#define CFG_DISABLE_READ_BUFFER (1 << 11)
|
||||
#define CFG_ENABLE_HANG_DETECT (1 << 12)
|
||||
#define CFG_FULL_LINE_DIRTY (1 << 13)
|
||||
#define CFG_TAG_CHK_ABRT_ON_ERR (1 << 14)
|
||||
#define CFG_TAG_CHK_CLR_ERR (1 << 15)
|
||||
#define CFG_DISABLE_SAMELINE (1 << 16)
|
||||
#define CFG_OBS_BUS_EN (1 << 31)
|
||||
#define CFG_DISABLE_WRITE_BUFFER BIT(10)
|
||||
#define CFG_DISABLE_READ_BUFFER BIT(11)
|
||||
#define CFG_ENABLE_HANG_DETECT BIT(12)
|
||||
#define CFG_FULL_LINE_DIRTY BIT(13)
|
||||
#define CFG_TAG_CHK_ABRT_ON_ERR BIT(14)
|
||||
#define CFG_TAG_CHK_CLR_ERR BIT(15)
|
||||
#define CFG_DISABLE_SAMELINE BIT(16)
|
||||
#define CFG_OBS_BUS_EN BIT(31)
|
||||
|
||||
#define BPMP_CACHE_LOCK 0x4
|
||||
#define LOCK_LINE(x) (1 << (x))
|
||||
#define LOCK_LINE(x) BIT((x))
|
||||
|
||||
#define BPMP_CACHE_SIZE 0xC
|
||||
#define BPMP_CACHE_LFSR 0x10
|
||||
|
||||
#define BPMP_CACHE_TAG_STATUS 0x14
|
||||
#define TAG_STATUS_TAG_CHECK_ERROR (1 << 0)
|
||||
#define TAG_STATUS_TAG_CHECK_ERROR BIT(0)
|
||||
#define TAG_STATUS_CONFLICT_ADDR_MASK 0xFFFFFFE0
|
||||
|
||||
#define BPMP_CACHE_CLKEN_OVERRIDE 0x18
|
||||
#define CLKEN_OVERRIDE_WR_MCCIF_CLKEN (1 << 0)
|
||||
#define CLKEN_OVERRIDE_RD_MCCIF_CLKEN (1 << 1)
|
||||
#define CLKEN_OVERRIDE_WR_MCCIF_CLKEN BIT(0)
|
||||
#define CLKEN_OVERRIDE_RD_MCCIF_CLKEN BIT(1)
|
||||
|
||||
#define BPMP_CACHE_MAINT_ADDR 0x20
|
||||
#define BPMP_CACHE_MAINT_DATA 0x24
|
||||
|
|
@ -68,8 +68,8 @@
|
|||
#define BPMP_CACHE_INT_CLEAR 0x44
|
||||
#define BPMP_CACHE_INT_RAW_EVENT 0x48
|
||||
#define BPMP_CACHE_INT_STATUS 0x4C
|
||||
#define INT_MAINT_DONE (1 << 0)
|
||||
#define INT_MAINT_ERROR (1 << 1)
|
||||
#define INT_MAINT_DONE BIT(0)
|
||||
#define INT_MAINT_ERROR BIT(1)
|
||||
|
||||
#define BPMP_CACHE_RB_CFG 0x80
|
||||
#define BPMP_CACHE_WB_CFG 0x84
|
||||
|
|
@ -78,12 +78,12 @@
|
|||
#define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
|
||||
|
||||
#define BPMP_CACHE_MMU_CFG 0xAC
|
||||
#define MMU_CFG_BLOCK_MAIN_ENTRY_WR (1 << 0)
|
||||
#define MMU_CFG_SEQ_EN (1 << 1)
|
||||
#define MMU_CFG_TLB_EN (1 << 2)
|
||||
#define MMU_CFG_SEG_CHECK_ALL_ENTRIES (1 << 3)
|
||||
#define MMU_CFG_ABORT_STORE_LAST (1 << 4)
|
||||
#define MMU_CFG_CLR_ABORT (1 << 5)
|
||||
#define MMU_CFG_BLOCK_MAIN_ENTRY_WR BIT(0)
|
||||
#define MMU_CFG_SEQ_EN BIT(1)
|
||||
#define MMU_CFG_TLB_EN BIT(2)
|
||||
#define MMU_CFG_SEG_CHECK_ALL_ENTRIES BIT(3)
|
||||
#define MMU_CFG_ABORT_STORE_LAST BIT(4)
|
||||
#define MMU_CFG_CLR_ABORT BIT(5)
|
||||
|
||||
#define BPMP_CACHE_MMU_CMD 0xB0
|
||||
#define MMU_CMD_NOP 0
|
||||
|
|
@ -98,25 +98,25 @@
|
|||
#define ABORT_STAT_UNIT_TLB 3
|
||||
#define ABORT_STAT_UNIT_SEG 4
|
||||
#define ABORT_STAT_UNIT_FALLBACK 5
|
||||
#define ABORT_STAT_OVERLAP (1 << 3)
|
||||
#define ABORT_STAT_OVERLAP BIT(3)
|
||||
#define ABORT_STAT_ENTRY (0x1F << 4)
|
||||
#define ABORT_STAT_TYPE_MASK (3 << 16)
|
||||
#define ABORT_STAT_TYPE_EXE (0 << 16)
|
||||
#define ABORT_STAT_TYPE_RD (1 << 16)
|
||||
#define ABORT_STAT_TYPE_WR (2 << 16)
|
||||
#define ABORT_STAT_SIZE (3 << 18)
|
||||
#define ABORT_STAT_SEQ (1 << 20)
|
||||
#define ABORT_STAT_PROT (1 << 21)
|
||||
#define ABORT_STAT_SEQ BIT(20)
|
||||
#define ABORT_STAT_PROT BIT(21)
|
||||
|
||||
#define BPMP_CACHE_MMU_ABORT_ADDR 0xB8
|
||||
#define BPMP_CACHE_MMU_ACTIVE_ENTRIES 0xBC
|
||||
|
||||
#define BPMP_MMU_SHADOW_ENTRY_BASE (BPMP_CACHE_BASE + 0x400)
|
||||
#define BPMP_MMU_MAIN_ENTRY_BASE (BPMP_CACHE_BASE + 0x800)
|
||||
#define MMU_EN_CACHED (1 << 0)
|
||||
#define MMU_EN_EXEC (1 << 1)
|
||||
#define MMU_EN_READ (1 << 2)
|
||||
#define MMU_EN_WRITE (1 << 3)
|
||||
#define MMU_EN_CACHED BIT(0)
|
||||
#define MMU_EN_EXEC BIT(1)
|
||||
#define MMU_EN_READ BIT(2)
|
||||
#define MMU_EN_WRITE BIT(3)
|
||||
|
||||
bpmp_mmu_entry_t mmu_entries[] =
|
||||
{
|
||||
|
|
@ -153,7 +153,7 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
|
|||
mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
|
||||
mmu_entry->attr = entry->attr;
|
||||
|
||||
BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
|
||||
BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= BIT(idx);
|
||||
|
||||
if (apply)
|
||||
BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
void _ccplex_enable_power()
|
||||
{
|
||||
u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~(1 << 5)); // Disable GPIO5 pinmuxing.
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~BIT(5)); // Disable GPIO5 pinmuxing.
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
|
||||
|
||||
// Enable cores power.
|
||||
|
|
|
|||
|
|
@ -20,17 +20,6 @@
|
|||
#include <storage/sdmmc.h>
|
||||
#include <utils/util.h>
|
||||
|
||||
/*
|
||||
* CLOCK Peripherals:
|
||||
* L 0 - 31
|
||||
* H 32 - 63
|
||||
* U 64 - 95
|
||||
* V 96 - 127
|
||||
* W 128 - 159
|
||||
* X 160 - 191
|
||||
* Y 192 - 223
|
||||
*/
|
||||
|
||||
/* clock_t: reset, enable, source, index, clk_src, clk_div */
|
||||
|
||||
static const clock_t _clock_uart[] = {
|
||||
|
|
@ -86,7 +75,7 @@ static clock_t _clock_coresight = {
|
|||
};
|
||||
|
||||
static clock_t _clock_pwm = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.2MHz.
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.4MHz. Stock PLLP / 54: 7.55MHz.
|
||||
};
|
||||
|
||||
static clock_t _clock_sdmmc_legacy_tm = {
|
||||
|
|
@ -96,30 +85,31 @@ static clock_t _clock_sdmmc_legacy_tm = {
|
|||
void clock_enable(const clock_t *clk)
|
||||
{
|
||||
// Put clock into reset.
|
||||
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
|
||||
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
|
||||
// Disable.
|
||||
CLOCK(clk->enable) &= ~(1 << clk->index);
|
||||
CLOCK(clk->enable) &= ~BIT(clk->index);
|
||||
// Configure clock source if required.
|
||||
if (clk->source)
|
||||
CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
|
||||
// Enable.
|
||||
CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
|
||||
CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index);
|
||||
usleep(2);
|
||||
|
||||
// Take clock off reset.
|
||||
CLOCK(clk->reset) &= ~(1 << clk->index);
|
||||
CLOCK(clk->reset) &= ~BIT(clk->index);
|
||||
}
|
||||
|
||||
void clock_disable(const clock_t *clk)
|
||||
{
|
||||
// Put clock into reset.
|
||||
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
|
||||
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index);
|
||||
// Disable.
|
||||
CLOCK(clk->enable) &= ~(1 << clk->index);
|
||||
CLOCK(clk->enable) &= ~BIT(clk->index);
|
||||
}
|
||||
|
||||
void clock_enable_fuse(bool enable)
|
||||
{
|
||||
// Enable Fuse registers visibility.
|
||||
CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
|
||||
}
|
||||
|
||||
|
|
@ -133,7 +123,7 @@ void clock_disable_uart(u32 idx)
|
|||
clock_disable(&_clock_uart[idx]);
|
||||
}
|
||||
|
||||
#define UART_SRC_CLK_DIV_EN (1 << 24)
|
||||
#define UART_SRC_CLK_DIV_EN BIT(24)
|
||||
|
||||
int clock_uart_use_src_div(u32 idx, u32 baud)
|
||||
{
|
||||
|
|
@ -281,7 +271,7 @@ void clock_enable_pllc(u32 divn)
|
|||
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
|
||||
|
||||
// Disable PLL and IDDQ in case they are on.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
|
||||
usleep(10);
|
||||
|
||||
|
|
@ -294,7 +284,7 @@ void clock_enable_pllc(u32 divn)
|
|||
;
|
||||
|
||||
// Disable PLLC_OUT1, enable reset and set div to 1.5.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = BIT(8);
|
||||
|
||||
// Enable PLLC_OUT1 and bring it out of reset.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
|
||||
|
|
@ -304,15 +294,15 @@ void clock_enable_pllc(u32 divn)
|
|||
void clock_disable_pllc()
|
||||
{
|
||||
// Disable PLLC and PLLC_OUT1.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
|
||||
usleep(10);
|
||||
}
|
||||
|
||||
#define PLLC4_ENABLED (1 << 31)
|
||||
#define PLLC4_ENABLED BIT(31)
|
||||
#define PLLC4_IN_USE (~PLLC4_ENABLED)
|
||||
|
||||
u32 pllc4_enabled = 0;
|
||||
|
|
@ -365,14 +355,14 @@ static void _clock_disable_pllc4(u32 mask)
|
|||
void clock_enable_pllu()
|
||||
{
|
||||
// Configure PLLU.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= (1 << 29); // Disable reference clock.
|
||||
u32 pllu_cfg = (CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & 0xFFE00000) | (1 << 24) | (1 << 16) | (0x19 << 8) | 2;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= BIT(29); // Disable reference clock.
|
||||
u32 pllu_cfg = (CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & 0xFFE00000) | BIT(24) | (1 << 16) | (0x19 << 8) | 2;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg;
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | (1 << 30); // Enable.
|
||||
CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | PLLCX_BASE_ENABLE; // Enable.
|
||||
|
||||
// Wait for PLL to stabilize.
|
||||
u32 timeout = (u32)TMR(TIMERUS_CNTR_1US) + 1300;
|
||||
while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & (1 << 27))) // PLL_LOCK.
|
||||
while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & PLLCX_BASE_LOCK)) // PLL_LOCK.
|
||||
if ((u32)TMR(TIMERUS_CNTR_1US) > timeout)
|
||||
break;
|
||||
usleep(10);
|
||||
|
|
@ -515,7 +505,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
|
|||
static void _clock_sdmmc_config_legacy_tm()
|
||||
{
|
||||
clock_t *clk = &_clock_sdmmc_legacy_tm;
|
||||
if (!(CLOCK(clk->enable) & (1 << clk->index)))
|
||||
if (!(CLOCK(clk->enable) & BIT(clk->index)))
|
||||
clock_enable(clk);
|
||||
}
|
||||
|
||||
|
|
@ -600,7 +590,7 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
|
|||
|
||||
// Enable PLLC4 if in use by any SDMMC.
|
||||
if (source)
|
||||
_clock_enable_pllc4(1 << id);
|
||||
_clock_enable_pllc4(BIT(id));
|
||||
|
||||
// Set SDMMC legacy timeout clock.
|
||||
_clock_sdmmc_config_legacy_tm();
|
||||
|
|
@ -724,5 +714,5 @@ void clock_sdmmc_disable(u32 id)
|
|||
_clock_sdmmc_set_reset(id);
|
||||
_clock_sdmmc_clear_enable(id);
|
||||
_clock_sdmmc_is_reset(id);
|
||||
_clock_disable_pllc4(1 << id);
|
||||
_clock_disable_pllc4(BIT(id));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -153,25 +153,25 @@
|
|||
#define CLK_NO_SOURCE 0x0
|
||||
|
||||
/*! PLL control and status bits */
|
||||
#define PLLCX_BASE_ENABLE (1 << 30)
|
||||
#define PLLCX_BASE_REF_DIS (1 << 29)
|
||||
#define PLLCX_BASE_LOCK (1 << 27)
|
||||
#define PLLCX_BASE_LOCK BIT(27)
|
||||
#define PLLCX_BASE_REF_DIS BIT(29)
|
||||
#define PLLCX_BASE_ENABLE BIT(30)
|
||||
|
||||
#define PLLA_BASE_IDDQ (1 << 25)
|
||||
#define PLLA_OUT0_CLKEN (1 << 1)
|
||||
#define PLLA_OUT0_RSTN_CLR (1 << 0)
|
||||
#define PLLA_OUT0_RSTN_CLR BIT(0)
|
||||
#define PLLA_OUT0_CLKEN BIT(1)
|
||||
#define PLLA_BASE_IDDQ BIT(25)
|
||||
|
||||
#define PLLC_MISC_RESET (1 << 30)
|
||||
#define PLLC_MISC1_IDDQ (1 << 27)
|
||||
#define PLLC_OUT1_CLKEN (1 << 1)
|
||||
#define PLLC_OUT1_RSTN_CLR (1 << 0)
|
||||
#define PLLC_OUT1_RSTN_CLR BIT(0)
|
||||
#define PLLC_OUT1_CLKEN BIT(1)
|
||||
#define PLLC_MISC1_IDDQ BIT(27)
|
||||
#define PLLC_MISC_RESET BIT(30)
|
||||
|
||||
#define PLLC4_MISC_EN_LCKDET (1 << 30)
|
||||
#define PLLC4_BASE_IDDQ (1 << 18)
|
||||
#define PLLC4_OUT3_CLKEN (1 << 1)
|
||||
#define PLLC4_OUT3_RSTN_CLR (1 << 0)
|
||||
#define PLLC4_OUT3_RSTN_CLR BIT(0)
|
||||
#define PLLC4_OUT3_CLKEN BIT(1)
|
||||
#define PLLC4_BASE_IDDQ BIT(18)
|
||||
#define PLLC4_MISC_EN_LCKDET BIT(30)
|
||||
|
||||
#define UTMIPLL_LOCK (1 << 31)
|
||||
#define UTMIPLL_LOCK BIT(31)
|
||||
|
||||
/*
|
||||
* CLOCK Peripherals:
|
||||
|
|
|
|||
|
|
@ -41,14 +41,14 @@
|
|||
#define GPIO_ANY_EDGE_CHANGE 1
|
||||
|
||||
/*! GPIO pins (0-7 for each port). */
|
||||
#define GPIO_PIN_0 (1 << 0)
|
||||
#define GPIO_PIN_1 (1 << 1)
|
||||
#define GPIO_PIN_2 (1 << 2)
|
||||
#define GPIO_PIN_3 (1 << 3)
|
||||
#define GPIO_PIN_4 (1 << 4)
|
||||
#define GPIO_PIN_5 (1 << 5)
|
||||
#define GPIO_PIN_6 (1 << 6)
|
||||
#define GPIO_PIN_7 (1 << 7)
|
||||
#define GPIO_PIN_0 BIT(0)
|
||||
#define GPIO_PIN_1 BIT(1)
|
||||
#define GPIO_PIN_2 BIT(2)
|
||||
#define GPIO_PIN_3 BIT(3)
|
||||
#define GPIO_PIN_4 BIT(4)
|
||||
#define GPIO_PIN_5 BIT(5)
|
||||
#define GPIO_PIN_6 BIT(6)
|
||||
#define GPIO_PIN_7 BIT(7)
|
||||
|
||||
/*! GPIO ports (A-EE). */
|
||||
#define GPIO_PORT_A 0
|
||||
|
|
|
|||
|
|
@ -281,7 +281,7 @@ static void _config_regulators()
|
|||
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
|
||||
(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||
BIT(6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||
|
||||
// Configure all Flexible Power Sequencers.
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
|
||||
|
|
|
|||
|
|
@ -20,18 +20,18 @@
|
|||
#include <soc/i2c.h>
|
||||
#include <utils/util.h>
|
||||
|
||||
#define I2C_PACKET_PROT_I2C (1 << 4)
|
||||
#define I2C_HEADER_CONT_XFER (1 << 15)
|
||||
#define I2C_HEADER_REP_START (1 << 16)
|
||||
#define I2C_HEADER_IE_ENABLE (1 << 17)
|
||||
#define I2C_HEADER_READ (1 << 19)
|
||||
#define I2C_PACKET_PROT_I2C BIT(4)
|
||||
#define I2C_HEADER_CONT_XFER BIT(15)
|
||||
#define I2C_HEADER_REP_START BIT(16)
|
||||
#define I2C_HEADER_IE_ENABLE BIT(17)
|
||||
#define I2C_HEADER_READ BIT(19)
|
||||
|
||||
#define I2C_CNFG (0x00 / 4)
|
||||
#define CMD1_WRITE (0 << 6)
|
||||
#define CMD1_READ (1 << 6)
|
||||
#define NORMAL_MODE_GO (1 << 9)
|
||||
#define PACKET_MODE_GO (1 << 10)
|
||||
#define NEW_MASTER_FSM (1 << 11)
|
||||
#define CMD1_READ BIT(6)
|
||||
#define NORMAL_MODE_GO BIT(9)
|
||||
#define PACKET_MODE_GO BIT(10)
|
||||
#define NEW_MASTER_FSM BIT(11)
|
||||
#define DEBOUNCE_CNT_4T (2 << 12)
|
||||
|
||||
#define I2C_CMD_ADDR0 (0x04 / 4)
|
||||
|
|
@ -43,14 +43,14 @@
|
|||
|
||||
#define I2C_STATUS (0x1C / 4)
|
||||
#define I2C_STATUS_NOACK (0xF << 0)
|
||||
#define I2C_STATUS_BUSY (1 << 8)
|
||||
#define I2C_STATUS_BUSY BIT(8)
|
||||
|
||||
#define I2C_TX_FIFO (0x50 / 4)
|
||||
#define I2C_RX_FIFO (0x54 / 4)
|
||||
|
||||
#define I2C_FIFO_CONTROL (0x5C / 4)
|
||||
#define RX_FIFO_FLUSH (1 << 0)
|
||||
#define TX_FIFO_FLUSH (1 << 1)
|
||||
#define RX_FIFO_FLUSH BIT(0)
|
||||
#define TX_FIFO_FLUSH BIT(1)
|
||||
|
||||
#define I2C_FIFO_STATUS (0x60 / 4)
|
||||
#define RX_FIFO_FULL_CNT (0xF << 0)
|
||||
|
|
@ -59,27 +59,27 @@
|
|||
#define I2C_INT_EN (0x64 / 4)
|
||||
#define I2C_INT_STATUS (0x68 / 4)
|
||||
#define I2C_INT_SOURCE (0x70 / 4)
|
||||
#define RX_FIFO_DATA_REQ (1 << 0)
|
||||
#define TX_FIFO_DATA_REQ (1 << 1)
|
||||
#define ARB_LOST (1 << 2)
|
||||
#define NO_ACK (1 << 3)
|
||||
#define RX_FIFO_UNDER (1 << 4)
|
||||
#define TX_FIFO_OVER (1 << 5)
|
||||
#define ALL_PACKETS_COMPLETE (1 << 6)
|
||||
#define PACKET_COMPLETE (1 << 7)
|
||||
#define BUS_CLEAR_DONE (1 << 11)
|
||||
#define RX_FIFO_DATA_REQ BIT(0)
|
||||
#define TX_FIFO_DATA_REQ BIT(1)
|
||||
#define ARB_LOST BIT(2)
|
||||
#define NO_ACK BIT(3)
|
||||
#define RX_FIFO_UNDER BIT(4)
|
||||
#define TX_FIFO_OVER BIT(5)
|
||||
#define ALL_PACKETS_COMPLETE BIT(6)
|
||||
#define PACKET_COMPLETE BIT(7)
|
||||
#define BUS_CLEAR_DONE BIT(11)
|
||||
|
||||
#define I2C_CLK_DIVISOR (0x6C / 4)
|
||||
|
||||
#define I2C_BUS_CLEAR_CONFIG (0x84 / 4)
|
||||
#define BC_ENABLE (1 << 0)
|
||||
#define BC_TERMINATE (1 << 1)
|
||||
#define BC_ENABLE BIT(0)
|
||||
#define BC_TERMINATE BIT(1)
|
||||
|
||||
#define I2C_BUS_CLEAR_STATUS (0x88 / 4)
|
||||
|
||||
#define I2C_CONFIG_LOAD (0x8C / 4)
|
||||
#define MSTR_CONFIG_LOAD (1 << 0)
|
||||
#define TIMEOUT_CONFIG_LOAD (1 << 2)
|
||||
#define MSTR_CONFIG_LOAD BIT(0)
|
||||
#define TIMEOUT_CONFIG_LOAD BIT(2)
|
||||
|
||||
static const u32 i2c_addrs[] = {
|
||||
0x7000C000, // I2C_1.
|
||||
|
|
@ -92,7 +92,7 @@ static const u32 i2c_addrs[] = {
|
|||
|
||||
static void _i2c_load_cfg_wait(vu32 *base)
|
||||
{
|
||||
base[I2C_CONFIG_LOAD] = (1 << 5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD;
|
||||
base[I2C_CONFIG_LOAD] = BIT(5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD;
|
||||
for (u32 i = 0; i < 20; i++)
|
||||
{
|
||||
usleep(1);
|
||||
|
|
@ -136,7 +136,7 @@ static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
|
|||
// Initiate transaction on normal mode.
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
|
||||
|
||||
u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
|
||||
u32 timeout = get_tmr_ms() + 400; // Actual for max 8 bytes at 100KHz is 0.74ms.
|
||||
while (base[I2C_STATUS] & I2C_STATUS_BUSY)
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
|
|
@ -168,7 +168,7 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
|
|||
// Initiate transaction on normal mode.
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
|
||||
|
||||
u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
|
||||
u32 timeout = get_tmr_ms() + 400; // Actual for max 8 bytes at 100KHz is 0.74ms.
|
||||
while (base[I2C_STATUS] & I2C_STATUS_BUSY)
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ static void _irq_enable_source(u32 irq)
|
|||
u32 bit = irq % 32;
|
||||
|
||||
// Set as normal IRQ.
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~(1 << bit);
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~BIT(bit);
|
||||
|
||||
// Enable IRQ source.
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = 1 << bit;
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = BIT(bit);
|
||||
}
|
||||
|
||||
static void _irq_disable_source(u32 irq)
|
||||
|
|
@ -59,7 +59,7 @@ static void _irq_disable_source(u32 irq)
|
|||
u32 bit = irq % 32;
|
||||
|
||||
// Disable IRQ source.
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = 1 << bit;
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = BIT(bit);
|
||||
}
|
||||
|
||||
static void _irq_disable_and_ack_all()
|
||||
|
|
@ -79,7 +79,7 @@ static void _irq_ack_source(u32 irq)
|
|||
u32 bit = irq % 32;
|
||||
|
||||
// Force stop the interrupt as it's serviced here.
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = 1 << bit;
|
||||
ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = BIT(bit);
|
||||
}
|
||||
|
||||
void irq_free(u32 irq)
|
||||
|
|
|
|||
|
|
@ -209,8 +209,8 @@ typedef enum _irq_status_t
|
|||
typedef enum _irq_flags_t
|
||||
{
|
||||
IRQ_FLAG_NONE = 0,
|
||||
IRQ_FLAG_ONE_OFF = (1 << 0),
|
||||
IRQ_FLAG_REPLACEABLE = (1 << 1)
|
||||
IRQ_FLAG_ONE_OFF = BIT(0),
|
||||
IRQ_FLAG_REPLACEABLE = BIT(1)
|
||||
} irq_flags_t;
|
||||
|
||||
void irq_end();
|
||||
|
|
|
|||
|
|
@ -19,16 +19,16 @@
|
|||
|
||||
#include <utils/types.h>
|
||||
|
||||
#define KFUSE_STATE_SOFTRESET (1 << 31)
|
||||
#define KFUSE_STATE_STOP (1 << 25)
|
||||
#define KFUSE_STATE_RESTART (1 << 24)
|
||||
#define KFUSE_STATE_CRCPASS (1 << 17)
|
||||
#define KFUSE_STATE_DONE (1 << 16)
|
||||
#define KFUSE_STATE_ERRBLOCK_MASK 0x3F00
|
||||
#define KFUSE_STATE_ERRBLOCK_SHIFT 8
|
||||
#define KFUSE_STATE_CURBLOCK_MASK 0x3F
|
||||
#define KFUSE_STATE_ERRBLOCK_SHIFT 8
|
||||
#define KFUSE_STATE_ERRBLOCK_MASK 0x3F00
|
||||
#define KFUSE_STATE_DONE BIT(16)
|
||||
#define KFUSE_STATE_CRCPASS BIT(17)
|
||||
#define KFUSE_STATE_RESTART BIT(24)
|
||||
#define KFUSE_STATE_STOP BIT(25)
|
||||
#define KFUSE_STATE_SOFTRESET BIT(31)
|
||||
|
||||
#define KFUSE_KEYADDR_AUTOINC (1<<16)
|
||||
#define KFUSE_KEYADDR_AUTOINC BIT(16)
|
||||
|
||||
#define KFUSE_STATE 0x80
|
||||
#define KFUSE_KEYADDR 0x88
|
||||
|
|
|
|||
|
|
@ -87,17 +87,18 @@
|
|||
#define PINMUX_PULL_DOWN (1 << 2)
|
||||
#define PINMUX_PULL_UP (2 << 2)
|
||||
|
||||
#define PINMUX_TRISTATE (1 << 4)
|
||||
#define PINMUX_PARKED (1 << 5)
|
||||
#define PINMUX_INPUT_ENABLE (1 << 6)
|
||||
#define PINMUX_LOCK (1 << 7)
|
||||
#define PINMUX_LPDR (1 << 8)
|
||||
#define PINMUX_HSM (1 << 9)
|
||||
#define PINMUX_TRISTATE BIT(4)
|
||||
#define PINMUX_PARKED BIT(5)
|
||||
#define PINMUX_INPUT_ENABLE BIT(6)
|
||||
#define PINMUX_LOCK BIT(7)
|
||||
#define PINMUX_LPDR BIT(8)
|
||||
#define PINMUX_HSM BIT(9)
|
||||
|
||||
#define PINMUX_IO_HV (1 << 10)
|
||||
#define PINMUX_OPEN_DRAIN (1 << 11)
|
||||
#define PINMUX_SCHMT (1 << 12)
|
||||
#define PINMUX_IO_HV BIT(10)
|
||||
#define PINMUX_OPEN_DRAIN BIT(11)
|
||||
#define PINMUX_SCHMT BIT(12)
|
||||
|
||||
#define PINMUX_DRIVE_MASK (3 << 13)
|
||||
#define PINMUX_DRIVE_1X (0 << 13)
|
||||
#define PINMUX_DRIVE_2X (1 << 13)
|
||||
#define PINMUX_DRIVE_3X (2 << 13)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
int pmc_enable_partition(u32 part, int enable)
|
||||
{
|
||||
u32 part_mask = 1 << part;
|
||||
u32 part_mask = BIT(part);
|
||||
u32 desired_state = enable << part;
|
||||
|
||||
// Check if the partition has the state we want.
|
||||
|
|
|
|||
|
|
@ -23,27 +23,27 @@
|
|||
|
||||
/*! PMC registers. */
|
||||
#define APBDEV_PMC_CNTRL 0x0
|
||||
#define PMC_CNTRL_MAIN_RST (1 << 4)
|
||||
#define PMC_CNTRL_MAIN_RST BIT(4)
|
||||
#define APBDEV_PMC_SEC_DISABLE 0x4
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
|
||||
#define APBDEV_PMC_PWRGATE_STATUS 0x38
|
||||
#define APBDEV_PMC_NO_IOPOWER 0x44
|
||||
#define PMC_NO_IOPOWER_GPIO_IO_EN (1 << 21)
|
||||
#define PMC_NO_IOPOWER_AUDIO_HV (1 << 18)
|
||||
#define PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12)
|
||||
#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
|
||||
#define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
|
||||
#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
|
||||
#define APBDEV_PMC_SCRATCH0 0x50
|
||||
#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
|
||||
#define PMC_SCRATCH0_MODE_FASTBOOT (1 << 30)
|
||||
#define PMC_SCRATCH0_MODE_PAYLOAD (1 << 29)
|
||||
#define PMC_SCRATCH0_MODE_RCM (1 << 1)
|
||||
#define PMC_SCRATCH0_MODE_WARMBOOT (1 << 0)
|
||||
#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
|
||||
#define PMC_SCRATCH0_MODE_RCM BIT(1)
|
||||
#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
|
||||
#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
|
||||
#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
|
||||
#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | PMC_SCRATCH0_MODE_FASTBOOT | PMC_SCRATCH0_MODE_PAYLOAD)
|
||||
#define APBDEV_PMC_SCRATCH1 0x54
|
||||
#define APBDEV_PMC_SCRATCH20 0xA0
|
||||
#define APBDEV_PMC_PWR_DET_VAL 0xE4
|
||||
#define PMC_PWR_DET_GPIO_IO_EN (1 << 21)
|
||||
#define PMC_PWR_DET_AUDIO_HV (1 << 18)
|
||||
#define PMC_PWR_DET_SDMMC1_IO_EN (1 << 12)
|
||||
#define PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
|
||||
#define PMC_PWR_DET_AUDIO_HV BIT(18)
|
||||
#define PMC_PWR_DET_GPIO_IO_EN BIT(21)
|
||||
#define APBDEV_PMC_DDR_PWR 0xE8
|
||||
#define APBDEV_PMC_USB_AO 0xF0
|
||||
#define APBDEV_PMC_CRYPTO_OP 0xF4
|
||||
|
|
@ -51,14 +51,15 @@
|
|||
#define PMC_CRYPTO_OP_SE_DISABLE 1
|
||||
#define APBDEV_PMC_SCRATCH33 0x120
|
||||
#define APBDEV_PMC_SCRATCH37 0x130
|
||||
#define PMC_SCRATCH37_KERNEL_PANIC_FLAG (1 << 24)
|
||||
#define PMC_SCRATCH37_KERNEL_PANIC_FLAG BIT(24)
|
||||
#define APBDEV_PMC_SCRATCH40 0x13C
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
|
||||
#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
|
||||
#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
|
||||
#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN (1 << 2)
|
||||
#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
|
||||
#define APBDEV_PMC_RST_STATUS 0x1B4
|
||||
#define APBDEV_PMC_IO_DPD_REQ 0x1B8
|
||||
#define PMC_IO_DPD_REQ_DPD_OFF BIT(30)
|
||||
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
|
||||
#define APBDEV_PMC_VDDP_SEL 0x1CC
|
||||
#define APBDEV_PMC_DDR_CFG 0x1D0
|
||||
|
|
|
|||
|
|
@ -150,30 +150,32 @@
|
|||
/*! AHB Gizmo registers. */
|
||||
#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
|
||||
#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29)
|
||||
#define PRIORITY_SELECT_USB BIT(6)
|
||||
#define PRIORITY_SELECT_USB2 BIT(18)
|
||||
#define PRIORITY_SELECT_USB3 BIT(17)
|
||||
#define PRIORITY_SELECT_USB BIT(6) // USB-OTG.
|
||||
#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC.
|
||||
#define PRIORITY_SELECT_USB3 BIT(17) // XUSB.
|
||||
#define AHB_GIZMO_AHB_MEM 0x10
|
||||
#define AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
|
||||
#define AHB_MEM_DONT_SPLIT_AHB_WR (1 << 7)
|
||||
#define AHB_MEM_IMMEDIATE (1 << 18)
|
||||
#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2)
|
||||
#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7)
|
||||
#define AHB_MEM_IMMEDIATE BIT(18)
|
||||
#define AHB_GIZMO_APB_DMA 0x14
|
||||
#define AHB_GIZMO_USB 0x20
|
||||
#define AHB_GIZMO_SDMMC4 0x48
|
||||
#define AHB_GIZMO_USB2 0x7C
|
||||
#define AHB_GIZMO_USB3 0x80
|
||||
#define AHB_GIZMO_IMMEDIATE (1 << 18)
|
||||
#define AHB_GIZMO_IMMEDIATE BIT(18)
|
||||
#define AHB_ARBITRATION_XBAR_CTRL 0xE0
|
||||
#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4
|
||||
#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8
|
||||
#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
|
||||
#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4
|
||||
#define MST_ID(x) (((x) & 0x1F) << 26)
|
||||
#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5)
|
||||
#define MEM_PREFETCH_USB_MST_ID MST_ID(6)
|
||||
#define MEM_PREFETCH_USB2_MST_ID MST_ID(18)
|
||||
#define MEM_PREFETCH_USB3_MST_ID MST_ID(17)
|
||||
#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG.
|
||||
#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC.
|
||||
#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB.
|
||||
#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21)
|
||||
#define MEM_PREFETCH_ENABLE (1 << 31)
|
||||
#define MEM_PREFETCH_ENABLE BIT(31)
|
||||
#define AHB_AHB_SPARE_REG 0x110
|
||||
|
||||
/*! Misc registers. */
|
||||
#define APB_MISC_PP_STRAPPING_OPT_A 0x08
|
||||
|
|
@ -190,16 +192,12 @@
|
|||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
|
||||
|
||||
/*! System registers. */
|
||||
#define AHB_ARBITRATION_XBAR_CTRL 0xE0
|
||||
#define AHB_AHB_SPARE_REG 0x110
|
||||
|
||||
/*! Secure boot registers. */
|
||||
#define SB_CSR 0x0
|
||||
#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
|
||||
#define SB_CSR_PIROM_DISABLE (1 << 4)
|
||||
#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1)
|
||||
#define SB_CSR_PIROM_DISABLE BIT(4)
|
||||
#define SB_AA64_RESET_LOW 0x30
|
||||
#define SB_AA64_RST_AARCH64_MODE_EN (1 << 0)
|
||||
#define SB_AA64_RST_AARCH64_MODE_EN BIT(0)
|
||||
#define SB_AA64_RESET_HIGH 0x34
|
||||
|
||||
/*! SOR registers. */
|
||||
|
|
@ -234,20 +232,20 @@
|
|||
#define TIMERUS_USEC_CFG (0x10 + 0x4)
|
||||
#define TIMER_TMR8_TMR_PTV 0x78
|
||||
#define TIMER_TMR9_TMR_PTV 0x80
|
||||
#define TIMER_EN (1 << 31)
|
||||
#define TIMER_PER_EN (1 << 30)
|
||||
#define TIMER_PER_EN BIT(30)
|
||||
#define TIMER_EN BIT(31)
|
||||
#define TIMER_TMR8_TMR_PCR 0x7C
|
||||
#define TIMER_TMR9_TMR_PCR 0x8C
|
||||
#define TIMER_INTR_CLR (1 << 30)
|
||||
#define TIMER_INTR_CLR BIT(30)
|
||||
|
||||
#define TIMER_WDT4_CONFIG (0x100 + 0x80)
|
||||
#define TIMER_SRC(TMR) (TMR & 0xF)
|
||||
#define TIMER_PER(PER) ((PER & 0xFF) << 4)
|
||||
#define TIMER_SYSRESET_EN (1 << 14)
|
||||
#define TIMER_PMCRESET_EN (1 << 15)
|
||||
#define TIMER_SRC(TMR) ((TMR) & 0xF)
|
||||
#define TIMER_PER(PER) (((PER) & 0xFF) << 4)
|
||||
#define TIMER_SYSRESET_EN BIT(14)
|
||||
#define TIMER_PMCRESET_EN BIT(15)
|
||||
#define TIMER_WDT4_COMMAND (0x108 + 0x80)
|
||||
#define TIMER_START_CNT (1 << 0)
|
||||
#define TIMER_CNT_DISABLE (1 << 1)
|
||||
#define TIMER_START_CNT BIT(0)
|
||||
#define TIMER_CNT_DISABLE BIT(1)
|
||||
#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
|
||||
#define TIMER_MAGIC_PTRN 0xC45A
|
||||
|
||||
|
|
@ -262,29 +260,29 @@
|
|||
#define I2S4_CTRL 0x3A0
|
||||
#define I2S5_CG 0x488
|
||||
#define I2S5_CTRL 0x4A0
|
||||
#define I2S_CG_SLCG_ENABLE (1 << 0)
|
||||
#define I2S_CTRL_MASTER_EN (1 << 10)
|
||||
#define I2S_CG_SLCG_ENABLE BIT(0)
|
||||
#define I2S_CTRL_MASTER_EN BIT(10)
|
||||
|
||||
/*! PWM registers. */
|
||||
#define PWM_CONTROLLER_PWM_CSR_0 0x00
|
||||
#define PWM_CONTROLLER_PWM_CSR_1 0x10
|
||||
#define PWM_CSR_EN (1 << 31)
|
||||
#define PWM_CSR_EN BIT(31)
|
||||
|
||||
/*! Special registers. */
|
||||
#define EMC_SCRATCH0 0x324
|
||||
#define EMC_HEKA_UPD (1 << 30)
|
||||
#define EMC_SEPT_RUN (1 << 31)
|
||||
#define EMC_HEKA_UPD BIT(30)
|
||||
#define EMC_SEPT_RUN BIT(31)
|
||||
|
||||
/*! Flow controller registers. */
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
|
||||
#define HALT_COP_GIC_IRQ (1 << 9)
|
||||
#define HALT_COP_LIC_IRQ (1 << 11)
|
||||
#define HALT_COP_SEC (1 << 23)
|
||||
#define HALT_COP_MSEC (1 << 24)
|
||||
#define HALT_COP_USEC (1 << 25)
|
||||
#define HALT_COP_JTAG (1 << 28)
|
||||
#define HALT_COP_WAIT_EVENT (1 << 30)
|
||||
#define HALT_COP_STOP_UNTIL_IRQ (1 << 31)
|
||||
#define HALT_COP_GIC_IRQ BIT(9)
|
||||
#define HALT_COP_LIC_IRQ BIT(11)
|
||||
#define HALT_COP_SEC BIT(23)
|
||||
#define HALT_COP_MSEC BIT(24)
|
||||
#define HALT_COP_USEC BIT(25)
|
||||
#define HALT_COP_JTAG BIT(28)
|
||||
#define HALT_COP_WAIT_EVENT BIT(30)
|
||||
#define HALT_COP_STOP_UNTIL_IRQ BIT(31)
|
||||
#define HALT_COP_MAX_CNT 0xFF
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
|
|
@ -297,9 +295,4 @@
|
|||
#define FLOW_CTLR_RAM_REPAIR 0x40
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
|
||||
|
||||
/*! USB controller registers. */
|
||||
#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
|
||||
#define BAT_CHRG_CFG0_OP_SRC_EN (1 << 3)
|
||||
#define BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2019 CTCaer
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2019 CTCaer
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
|
|||
|
|
@ -1167,7 +1167,7 @@ DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n",
|
|||
ums->cmnd[1] &= 0x1F; // Mask away the LUN.
|
||||
for (u32 i = 1; i < cmnd_size; ++i)
|
||||
{
|
||||
if (ums->cmnd[i] && !(mask & (1 << i)))
|
||||
if (ums->cmnd[i] && !(mask & BIT(i)))
|
||||
{
|
||||
ums->lun.sense_data = SS_INVALID_FIELD_IN_CDB;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,12 +23,12 @@
|
|||
|
||||
/* General USB registers */
|
||||
#define USB1_IF_USB_SUSP_CTRL 0x400
|
||||
#define SUSP_CTRL_USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
|
||||
#define SUSP_CTRL_USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
|
||||
#define SUSP_CTRL_USB_PHY_CLK_VALID (1 << 7)
|
||||
#define SUSP_CTRL_UTMIP_RESET (1 << 11)
|
||||
#define SUSP_CTRL_UTMIP_PHY_ENB (1 << 12)
|
||||
#define SUSP_CTRL_UTMIP_UTMIP_SUSPL1_SET (1 << 25)
|
||||
#define SUSP_CTRL_USB_WAKE_ON_CNNT_EN_DEV BIT(3)
|
||||
#define SUSP_CTRL_USB_WAKE_ON_DISCON_EN_DEV BIT(4)
|
||||
#define SUSP_CTRL_USB_PHY_CLK_VALID BIT(7)
|
||||
#define SUSP_CTRL_UTMIP_RESET BIT(11)
|
||||
#define SUSP_CTRL_UTMIP_PHY_ENB BIT(12)
|
||||
#define SUSP_CTRL_UTMIP_UTMIP_SUSPL1_SET BIT(25)
|
||||
#define USB1_IF_USB_PHY_VBUS_SENSORS 0x404
|
||||
#define USB1_UTMIP_XCVR_CFG0 0x808
|
||||
#define USB1_UTMIP_BIAS_CFG0 0x80C
|
||||
|
|
@ -37,6 +37,9 @@
|
|||
#define USB1_UTMIP_TX_CFG0 0x820
|
||||
#define USB1_UTMIP_MISC_CFG1 0x828
|
||||
#define USB1_UTMIP_DEBOUNCE_CFG0 0x82C
|
||||
#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
|
||||
#define BAT_CHRG_CFG0_PWRDOWN_CHRG BIT(0)
|
||||
#define BAT_CHRG_CFG0_OP_SRC_EN BIT(3)
|
||||
#define USB1_UTMIP_SPARE_CFG0 0x834
|
||||
#define USB1_UTMIP_XCVR_CFG1 0x838
|
||||
#define USB1_UTMIP_BIAS_CFG1 0x83C
|
||||
|
|
@ -46,38 +49,38 @@
|
|||
|
||||
/* USB Queue Head Descriptor */
|
||||
#define USB2_QH_USB2D_QH_EP_BASE (USB_BASE + 0x1000)
|
||||
#define USB_QHD_EP_CAP_IOS_ENABLE (1 << 15)
|
||||
#define USB_QHD_EP_CAP_IOS_ENABLE BIT(15)
|
||||
#define USB_QHD_EP_CAP_MAX_PKT_LEN_MASK 0x7FF
|
||||
#define USB_QHD_EP_CAP_ZERO_LEN_TERM_DIS (1 << 29)
|
||||
#define USB_QHD_EP_CAP_ZERO_LEN_TERM_DIS BIT(29)
|
||||
#define USB_QHD_EP_CAP_MULTI_NON_ISO (0 << 30)
|
||||
#define USB_QHD_EP_CAP_MULTI_1 (1 << 30)
|
||||
#define USB_QHD_EP_CAP_MULTI_2 (2 << 30)
|
||||
#define USB_QHD_EP_CAP_MULTI_3 (3 << 30)
|
||||
|
||||
#define USB_QHD_TOKEN_XFER_ERROR (1 << 3)
|
||||
#define USB_QHD_TOKEN_BUFFER_ERROR (1 << 5)
|
||||
#define USB_QHD_TOKEN_HALTED (1 << 6)
|
||||
#define USB_QHD_TOKEN_ACTIVE (1 << 7)
|
||||
#define USB_QHD_TOKEN_XFER_ERROR BIT(3)
|
||||
#define USB_QHD_TOKEN_BUFFER_ERROR BIT(5)
|
||||
#define USB_QHD_TOKEN_HALTED BIT(6)
|
||||
#define USB_QHD_TOKEN_ACTIVE BIT(7)
|
||||
#define USB_QHD_TOKEN_MULT_OVERR_MASK (2 << 10)
|
||||
#define USB_QHD_TOKEN_IRQ_ON_COMPLETE (1 << 15)
|
||||
#define USB_QHD_TOKEN_IRQ_ON_COMPLETE BIT(15)
|
||||
#define USB_QHD_TOKEN_TOTAL_BYTES_SHIFT 16
|
||||
|
||||
/* USB_OTG/USB_1 controllers register bits */
|
||||
#define USB2D_PORTSC1_SUSP (1 << 7)
|
||||
#define USB2D_PORTSC1_SUSP BIT(7)
|
||||
|
||||
#define USB2D_USBCMD_RUN (1 << 0)
|
||||
#define USB2D_USBCMD_RESET (1 << 1)
|
||||
#define USB2D_USBCMD_RUN BIT(0)
|
||||
#define USB2D_USBCMD_RESET BIT(1)
|
||||
#define USB2D_USBCMD_ITC_MASK (0xFF << 16)
|
||||
|
||||
#define USB2D_USBSTS_UI (1 << 0)
|
||||
#define USB2D_USBSTS_UEI (1 << 1)
|
||||
#define USB2D_USBSTS_PCI (1 << 2)
|
||||
#define USB2D_USBSTS_FRI (1 << 3)
|
||||
#define USB2D_USBSTS_SEI (1 << 4)
|
||||
#define USB2D_USBSTS_AAI (1 << 5)
|
||||
#define USB2D_USBSTS_URI (1 << 6)
|
||||
#define USB2D_USBSTS_SRI (1 << 7)
|
||||
#define USB2D_USBSTS_SLI (1 << 8)
|
||||
#define USB2D_USBSTS_UI BIT(0)
|
||||
#define USB2D_USBSTS_UEI BIT(1)
|
||||
#define USB2D_USBSTS_PCI BIT(2)
|
||||
#define USB2D_USBSTS_FRI BIT(3)
|
||||
#define USB2D_USBSTS_SEI BIT(4)
|
||||
#define USB2D_USBSTS_AAI BIT(5)
|
||||
#define USB2D_USBSTS_URI BIT(6)
|
||||
#define USB2D_USBSTS_SRI BIT(7)
|
||||
#define USB2D_USBSTS_SLI BIT(8)
|
||||
|
||||
#define USB2D_USBMODE_CM_MASK (3 << 0)
|
||||
#define USB2D_USBMODE_CM_IDLE 0
|
||||
|
|
@ -85,33 +88,33 @@
|
|||
#define USB2D_USBMODE_CM_DEVICE 2
|
||||
#define USB2D_USBMODE_CM_HOST 3
|
||||
|
||||
#define USB2D_ENDPT_STATUS_RX_OFFSET (1 << 0)
|
||||
#define USB2D_ENDPT_STATUS_TX_OFFSET (1 << 16)
|
||||
#define USB2D_ENDPT_STATUS_RX_OFFSET BIT(0)
|
||||
#define USB2D_ENDPT_STATUS_TX_OFFSET BIT(16)
|
||||
|
||||
#define USB2D_ENDPTCTRL_RX_EP_STALL (1 << 0)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_STALL BIT(0)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_TYPE_CTRL (0 << 2)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_TYPE_ISO (1 << 2)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_TYPE_BULK (2 << 2)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_TYPE_INTR (3 << 2)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_TYPE_MASK (3 << 2)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_INHIBIT (1 << 5)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_RESET (1 << 6)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_ENABLE (1 << 7)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_STALL (1 << 16)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_INHIBIT BIT(5)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_RESET BIT(6)
|
||||
#define USB2D_ENDPTCTRL_RX_EP_ENABLE BIT(7)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_STALL BIT(16)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_TYPE_CTRL (0 << 18)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_TYPE_ISO (1 << 18)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_TYPE_BULK (2 << 18)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_TYPE_INTR (3 << 18)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_TYPE_MASK (3 << 18)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_INHIBIT (1 << 21)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_RESET (1 << 22)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_ENABLE (1 << 23)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_INHIBIT BIT(21)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_RESET BIT(22)
|
||||
#define USB2D_ENDPTCTRL_TX_EP_ENABLE BIT(23)
|
||||
|
||||
#define USB2D_HOSTPC1_DEVLC_ASUS (1 << 17)
|
||||
#define USB2D_HOSTPC1_DEVLC_PHCD (1 << 22)
|
||||
#define USB2D_HOSTPC1_DEVLC_ASUS BIT(17)
|
||||
#define USB2D_HOSTPC1_DEVLC_PHCD BIT(22)
|
||||
#define USB2D_HOSTPC1_DEVLC_PSPD_MASK (3 << 25)
|
||||
|
||||
#define USB2D_OTGSC_USB_ID_PULLUP (1 << 5)
|
||||
#define USB2D_OTGSC_USB_ID_PULLUP BIT(5)
|
||||
#define USB2D_OTGSC_USB_IRQ_STS_MASK (0x7F << 16)
|
||||
|
||||
/* USB_OTG/USB_1 controllers registers */
|
||||
|
|
|
|||
|
|
@ -396,10 +396,10 @@ static void _usb_device_power_down()
|
|||
// A reset or clear of the PHCD suspend bit must happen.
|
||||
|
||||
// Power down OTG and Bias circuits.
|
||||
USB(USB1_UTMIP_BIAS_CFG0) |= (1 << 11) | (1 << 10); // UTMIP_OTGPD, UTMIP_BIASPD.
|
||||
USB(USB1_UTMIP_BIAS_CFG0) |= BIT(11) | BIT(10); // UTMIP_OTGPD, UTMIP_BIASPD.
|
||||
|
||||
// Power down ID detectors.
|
||||
USB(USB1_UTMIP_BIAS_CFG0) |= (1 << 23) | (1 << 22); //UTMIP_IDPD_SEL, UTMIP_IDPD_VAL.
|
||||
USB(USB1_UTMIP_BIAS_CFG0) |= BIT(23) | BIT(22); // UTMIP_IDPD_SEL, UTMIP_IDPD_VAL.
|
||||
|
||||
if (usbd_otg->charger_detect)
|
||||
{
|
||||
|
|
@ -409,21 +409,21 @@ static void _usb_device_power_down()
|
|||
|
||||
// Power down the UTMIP transceivers.
|
||||
// UTMIP_FORCE_PDZI_POWERDOWN, UTMIP_FORCE_PD2_POWERDOWN, UTMIP_FORCE_PD_POWERDOWN.
|
||||
USB(USB1_UTMIP_XCVR_CFG0) |= (1 << 18) | (1 << 16) |(1 << 14);
|
||||
USB(USB1_UTMIP_XCVR_CFG0) |= BIT(18) | BIT(16) |BIT(14);
|
||||
// UTMIP_FORCE_PDDR_POWERDOWN, UTMIP_FORCE_PDCHRP_POWERDOWN, UTMIP_FORCE_PDDISC_POWERDOWN.
|
||||
USB(USB1_UTMIP_XCVR_CFG1) |= (1 << 4) | (1 << 2) | (1 << 0);
|
||||
USB(USB1_UTMIP_XCVR_CFG1) |= BIT(4) | BIT(2) | BIT(0);
|
||||
|
||||
// Keep UTMIP in reset.
|
||||
USB(USB1_IF_USB_SUSP_CTRL) |= SUSP_CTRL_UTMIP_RESET;
|
||||
|
||||
// Power down PD trunk.
|
||||
USB(USB1_UTMIP_BIAS_CFG1) |= (1 << 0); //UTMIP_FORCE_PDTRK_POWERDOWN.
|
||||
USB(USB1_UTMIP_BIAS_CFG1) |= BIT(0); //UTMIP_FORCE_PDTRK_POWERDOWN.
|
||||
|
||||
// Force UTMIP_PLL power down.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= (1 << 14); // UTMIP_FORCE_PLL_ENABLE_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= (1 << 12); // UTMIP_FORCE_PLL_ACTIVE_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= (1 << 4) | (1 << 0); // UTMIP_FORCE_PD_SAMP_A/C_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= (1 << 16); // UTMIP_FORCE_PLLU_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= BIT(14); // UTMIP_FORCE_PLL_ENABLE_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= BIT(12); // UTMIP_FORCE_PLL_ACTIVE_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= BIT(4) | BIT(0); // UTMIP_FORCE_PD_SAMP_A/C_POWERDOWN.
|
||||
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) |= BIT(16); // UTMIP_FORCE_PLLU_POWERDOWN.
|
||||
|
||||
// Disable crystal clock.
|
||||
USB(USB1_UTMIP_MISC_CFG1) &= 0xBFFFFFFF;
|
||||
|
|
|
|||
|
|
@ -20,10 +20,10 @@
|
|||
|
||||
#include <utils/types.h>
|
||||
|
||||
#define BTN_POWER (1 << 0)
|
||||
#define BTN_VOL_DOWN (1 << 1)
|
||||
#define BTN_VOL_UP (1 << 2)
|
||||
#define BTN_SINGLE (1 << 7)
|
||||
#define BTN_POWER BIT(0)
|
||||
#define BTN_VOL_DOWN BIT(1)
|
||||
#define BTN_VOL_UP BIT(2)
|
||||
#define BTN_SINGLE BIT(7)
|
||||
|
||||
u8 btn_read();
|
||||
u8 btn_read_vol();
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -51,24 +52,30 @@ typedef volatile unsigned char vu8;
|
|||
typedef volatile unsigned short vu16;
|
||||
typedef volatile unsigned int vu32;
|
||||
|
||||
#ifdef __aarch64__
|
||||
typedef u64 uptr;
|
||||
#else /* __arm__ or __thumb__ */
|
||||
typedef u32 uptr;
|
||||
#endif
|
||||
|
||||
typedef int bool;
|
||||
#define true 1
|
||||
#define false 0
|
||||
|
||||
#define BOOT_CFG_AUTOBOOT_EN (1 << 0)
|
||||
#define BOOT_CFG_FROM_LAUNCH (1 << 1)
|
||||
#define BOOT_CFG_FROM_ID (1 << 2)
|
||||
#define BOOT_CFG_TO_EMUMMC (1 << 3)
|
||||
#define BOOT_CFG_SEPT_RUN (1 << 7)
|
||||
#define BOOT_CFG_AUTOBOOT_EN BIT(0)
|
||||
#define BOOT_CFG_FROM_LAUNCH BIT(1)
|
||||
#define BOOT_CFG_FROM_ID BIT(2)
|
||||
#define BOOT_CFG_TO_EMUMMC BIT(3)
|
||||
#define BOOT_CFG_SEPT_RUN BIT(7)
|
||||
|
||||
#define EXTRA_CFG_KEYS (1 << 0)
|
||||
#define EXTRA_CFG_PAYLOAD (1 << 1)
|
||||
#define EXTRA_CFG_MODULE (1 << 2)
|
||||
#define EXTRA_CFG_KEYS BIT(0)
|
||||
#define EXTRA_CFG_PAYLOAD BIT(1)
|
||||
#define EXTRA_CFG_MODULE BIT(2)
|
||||
|
||||
#define EXTRA_CFG_NYX_BIS (1 << 4)
|
||||
#define EXTRA_CFG_NYX_UMS (1 << 5)
|
||||
#define EXTRA_CFG_NYX_RELOAD (1 << 6)
|
||||
#define EXTRA_CFG_NYX_DUMP (1 << 7)
|
||||
#define EXTRA_CFG_NYX_BIS BIT(4)
|
||||
#define EXTRA_CFG_NYX_UMS BIT(5)
|
||||
#define EXTRA_CFG_NYX_RELOAD BIT(6)
|
||||
#define EXTRA_CFG_NYX_DUMP BIT(7)
|
||||
|
||||
typedef enum _nyx_ums_type
|
||||
{
|
||||
|
|
|
|||
|
|
@ -23,19 +23,19 @@
|
|||
|
||||
typedef enum
|
||||
{
|
||||
NYX_CFG_BIS = (1 << 5),
|
||||
NYX_CFG_UMS = (1 << 6),
|
||||
NYX_CFG_DUMP = (1 << 7),
|
||||
NYX_CFG_BIS = BIT(5),
|
||||
NYX_CFG_UMS = BIT(6),
|
||||
NYX_CFG_DUMP = BIT(7),
|
||||
} nyx_cfg_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERR_LIBSYS_LP0 = (1 << 0),
|
||||
ERR_SYSOLD_NYX = (1 << 1),
|
||||
ERR_LIBSYS_MTC = (1 << 2),
|
||||
ERR_SD_BOOT_EN = (1 << 3),
|
||||
ERR_L4T_KERNEL = (1 << 24),
|
||||
ERR_EXCEPTION = (1 << 31),
|
||||
ERR_LIBSYS_LP0 = BIT(0),
|
||||
ERR_SYSOLD_NYX = BIT(1),
|
||||
ERR_LIBSYS_MTC = BIT(2),
|
||||
ERR_SD_BOOT_EN = BIT(3),
|
||||
ERR_L4T_KERNEL = BIT(24),
|
||||
ERR_EXCEPTION = BIT(31),
|
||||
} hekate_errors_t;
|
||||
|
||||
#define byte_swap_32(num) ((((num) >> 24) & 0xff) | (((num) << 8) & 0xff0000) | \
|
||||
|
|
|
|||
|
|
@ -455,11 +455,11 @@ static int _dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t
|
|||
|
||||
typedef enum
|
||||
{
|
||||
PART_BOOT = (1 << 0),
|
||||
PART_SYSTEM = (1 << 1),
|
||||
PART_USER = (1 << 2),
|
||||
PART_RAW = (1 << 3),
|
||||
PART_GP_ALL = (1 << 7)
|
||||
PART_BOOT = BIT(0),
|
||||
PART_SYSTEM = BIT(1),
|
||||
PART_USER = BIT(2),
|
||||
PART_RAW = BIT(3),
|
||||
PART_GP_ALL = BIT(7)
|
||||
} emmcPartType_t;
|
||||
|
||||
static void _dump_emmc_selected(emmcPartType_t dumpType)
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ extern bool is_ipl_updated(void *buf, char *path, bool force);
|
|||
#define CNT_TYPE_KRN 10 // Kernel.
|
||||
|
||||
// FSS0 Content Flags.
|
||||
#define CNT_FLAG0_EXPERIMENTAL (1 << 0)
|
||||
#define CNT_FLAG0_EXPERIMENTAL BIT(0)
|
||||
|
||||
// FSS0 Meta Header.
|
||||
typedef struct _fss_meta_t
|
||||
|
|
|
|||
|
|
@ -124,20 +124,20 @@ typedef struct _atm_fatal_error_ctx
|
|||
} atm_fatal_error_ctx;
|
||||
|
||||
#define ATM_FATAL_ERR_CTX_ADDR 0x4003E000
|
||||
#define ATM_FATAL_MAGIC 0x30454641 // AFE0
|
||||
#define ATM_FATAL_MAGIC 0x30454641 // AFE0
|
||||
|
||||
#define ATM_WB_HEADER_OFF 0x244
|
||||
#define ATM_WB_MAGIC 0x30544257
|
||||
#define ATM_WB_HEADER_OFF 0x244
|
||||
#define ATM_WB_MAGIC 0x30544257 // WBT0
|
||||
|
||||
// Exosphère mailbox defines.
|
||||
#define EXO_CFG_ADDR 0x8000F000
|
||||
#define EXO_CFG_ADDR 0x8000F000
|
||||
#define EXO_MAGIC_VAL 0x304F5845
|
||||
#define EXO_FLAG_DBG_PRIV (1 << 1)
|
||||
#define EXO_FLAG_DBG_USER (1 << 2)
|
||||
#define EXO_FLAG_NO_USER_EXC (1 << 3)
|
||||
#define EXO_FLAG_USER_PMU (1 << 4)
|
||||
#define EXO_FLAG_CAL0_BLANKING (1 << 5)
|
||||
#define EXO_FLAG_CAL0_WRITES_SYS (1 << 6)
|
||||
#define EXO_FLAG_DBG_PRIV BIT(1)
|
||||
#define EXO_FLAG_DBG_USER BIT(2)
|
||||
#define EXO_FLAG_NO_USER_EXC BIT(3)
|
||||
#define EXO_FLAG_USER_PMU BIT(4)
|
||||
#define EXO_FLAG_CAL0_BLANKING BIT(5)
|
||||
#define EXO_FLAG_CAL0_WRITES_SYS BIT(6)
|
||||
|
||||
#define EXO_FW_VER(mj, mn, rv) (((mj) << 24) | ((mn) << 16) | ((rv) << 8))
|
||||
|
||||
|
|
|
|||
|
|
@ -22,11 +22,11 @@
|
|||
|
||||
typedef enum
|
||||
{
|
||||
PART_BOOT = (1 << 0),
|
||||
PART_SYSTEM = (1 << 1),
|
||||
PART_USER = (1 << 2),
|
||||
PART_RAW = (1 << 3),
|
||||
PART_GP_ALL = (1 << 7)
|
||||
PART_BOOT = BIT(0),
|
||||
PART_SYSTEM = BIT(1),
|
||||
PART_USER = BIT(2),
|
||||
PART_RAW = BIT(3),
|
||||
PART_GP_ALL = BIT(7)
|
||||
} emmcPartType_t;
|
||||
|
||||
void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui);
|
||||
|
|
|
|||
Loading…
Reference in a new issue