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bdk: manage host1x only in hw init
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parent
4da1d10553
commit
d0b22bf374
4 changed files with 8 additions and 7 deletions
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@ -379,8 +379,8 @@ void display_init()
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// Enable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
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@ -798,8 +798,8 @@ skip_panel_deinit:
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// Disable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_DISP1);
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// Power down pads.
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DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) |
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@ -539,7 +539,6 @@ int vic_init()
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// Ease the stress to APB.
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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clock_enable_host1x();
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clock_enable_vic();
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// Restore sys clock.
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@ -77,8 +77,6 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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// Enable clocks.
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clock_enable_host1x();
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usleep(2);
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clock_enable_tsec();
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clock_enable_sor_safe();
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clock_enable_sor0();
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@ -415,6 +415,9 @@ void hw_init()
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sdram_init();
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bpmp_mmu_enable();
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// Enable HOST1X used by every display module (DC, VIC, NVDEC, NVENC, TSEC, etc).
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clock_enable_host1x();
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}
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void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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@ -470,6 +473,7 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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break;
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default:
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display_end();
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clock_disable_host1x();
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}
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// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
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