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sdmmc: add support for sandisk emmc device report
This commit is contained in:
CTCaer
parent
e94bd23d6f
commit
dcdf687a07
3 changed files with 190 additions and 51 deletions
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@ -2,6 +2,7 @@
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* Header for MultiMediaCard (MMC)
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*
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* Copyright 2002 Hewlett-Packard Company
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* Copyright 2018-2021 CTCaer
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*
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* Use consistent with the GNU GPL is permitted,
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* provided that this copyright notice is
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@ -21,8 +22,8 @@
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* 15 May 2002
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*/
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#ifndef LINUX_MMC_MMC_H
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#define LINUX_MMC_MMC_H
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#ifndef MMC_H
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#define MMC_H
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/* Standard MMC commands (4.1) type argument response */
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/* class 1 */
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@ -97,29 +98,29 @@
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#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
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/*
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* MMC_SWITCH argument format:
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*
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* [31:26] Always 0
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* [25:24] Access Mode
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* [23:16] Location of target Byte in EXT_CSD
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* [15:08] Value Byte
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* [07:03] Always 0
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* [02:00] Command Set
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*/
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* MMC_SWITCH argument format:
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*
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* [31:26] Always 0
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* [25:24] Access Mode
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* [23:16] Location of target Byte in EXT_CSD
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* [15:08] Value Byte
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* [07:03] Always 0
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* [02:00] Command Set
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*/
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/*
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MMC status in R1, for native mode (SPI bits are different)
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Type
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e : error bit
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s : status bit
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r : detected and set for the actual command response
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x : detected and set during command execution. the host must poll
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the card by sending status command in order to read these bits.
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Clear condition
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a : according to the card state
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b : always related to the previous command. Reception of
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a valid command will clear it (with a delay of one command)
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c : clear by read
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* MMC status in R1, for native mode (SPI bits are different)
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* Type
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* e : error bit
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* s : status bit
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* r : detected and set for the actual command response
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* x : detected and set during command execution. the host must poll
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* the card by sending status command in order to read these bits.
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* Clear condition
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* a : according to the card state
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* b : always related to the previous command. Reception of a valid
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* command will clear it (with a delay of one command)
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* c : clear by read
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*/
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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@ -151,6 +152,7 @@ c : clear by read
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#define R1_AKE_SEQ_ERROR (1 << 3)
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/* R1_CURRENT_STATE 12:9 */
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#define R1_STATE(x) ((x) << 9)
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#define R1_STATE_IDLE 0
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#define R1_STATE_READY 1
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#define R1_STATE_IDENT 2
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@ -162,9 +164,9 @@ c : clear by read
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#define R1_STATE_DIS 8
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/*
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* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
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* R1 is the low order byte; R2 is the next highest byte, when present.
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*/
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* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
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* R1 is the low order byte; R2 is the next highest byte, when present.
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*/
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#define R1_SPI_IDLE (1 << 0)
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#define R1_SPI_ERASE_RESET (1 << 1)
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#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
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@ -185,16 +187,16 @@ c : clear by read
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#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
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/*
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* OCR bits are mostly in host.h
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*/
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* OCR bits are mostly in host.h
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*/
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#define MMC_CARD_VDD_18 (1 << 7) /* Card VDD voltage 1.8 */
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#define MMC_CARD_VDD_27_34 (0x7F << 15) /* Card VDD voltage 2.7 ~ 3.4 */
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#define MMC_CARD_CCS (1 << 30) /* Card Capacity status bit */
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#define MMC_CARD_BUSY (1 << 31) /* Card Power up status bit */
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/*
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* Card Command Classes (CCC)
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*/
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* Card Command Classes (CCC)
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*/
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#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
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/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
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/* (and for SPI, CMD58,59) */
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@ -222,8 +224,8 @@ c : clear by read
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/* (CMD?) */
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/*
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* CSD field definitions
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*/
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* CSD field definitions
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*/
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#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
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#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
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@ -237,8 +239,8 @@ c : clear by read
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#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
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/*
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* EXT_CSD fields
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*/
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* EXT_CSD fields
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*/
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#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
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#define EXT_CSD_FLUSH_CACHE 32 /* W */
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@ -316,8 +318,8 @@ c : clear by read
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#define EXT_CSD_HPI_FEATURES 503 /* RO */
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/*
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* EXT_CSD field definitions
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*/
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
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@ -393,8 +395,8 @@ c : clear by read
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#define EXT_CSD_PACKED_EVENT_EN (1<<3)
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/*
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* EXCEPTION_EVENT_STATUS field
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*/
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* EXCEPTION_EVENT_STATUS field
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*/
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#define EXT_CSD_URGENT_BKOPS (1<<0)
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#define EXT_CSD_DYNCAP_NEEDED (1<<1)
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#define EXT_CSD_SYSPOOL_EXHAUSTED (1<<2)
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@ -404,34 +406,34 @@ c : clear by read
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#define EXT_CSD_PACKED_INDEXED_ERROR (1<<1)
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/*
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* BKOPS status level
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*/
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* BKOPS status level
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*/
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#define EXT_CSD_BKOPS_LEVEL_2 0x2
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/*
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* BKOPS modes
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*/
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* BKOPS modes
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*/
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#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
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#define EXT_CSD_AUTO_BKOPS_MASK 0x02
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/*
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* Command Queue
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*/
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* Command Queue
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*/
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#define EXT_CSD_CMDQ_MODE_ENABLED (1<<0)
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#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
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#define EXT_CSD_CMDQ_SUPPORTED (1<<0)
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/*
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* MMC_SWITCH access modes
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*/
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* MMC_SWITCH access modes
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*/
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
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/*
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* Erase/trim/discard
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*/
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* Erase/trim/discard
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*/
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#define MMC_ERASE_ARG 0x00000000
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#define MMC_SECURE_ERASE_ARG 0x80000000
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#define MMC_TRIM_ARG 0x00000001
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@ -441,4 +443,9 @@ c : clear by read
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#define MMC_SECURE_ARGS 0x80000000
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#define MMC_TRIM_ARGS 0x00008001
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#endif /* LINUX_MMC_MMC_H */
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/*
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* Vendor definitions and structs
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*/
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#define MMC_SANDISK_HEALTH_REPORT 0x96C9D71C
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#endif /* MMC_H */
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@ -139,6 +139,60 @@ static int _sdmmc_storage_check_status(sdmmc_storage_t *storage)
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return _sdmmc_storage_get_status(storage, &tmp, 0);
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}
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int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg)
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{
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sdmmc_cmd_t cmdbuf;
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sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_62_CMD, arg, SDMMC_RSP_TYPE_1, 1);
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if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, 0, 0))
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return 0;
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u32 resp;
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sdmmc_get_rsp(storage->sdmmc, &resp, 4, SDMMC_RSP_TYPE_1);
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resp = -1;
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u32 timeout = get_tmr_ms() + 1500;
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while (resp != (R1_READY_FOR_DATA | R1_STATE(R1_STATE_TRAN)))
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{
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_sdmmc_storage_get_status(storage, &resp, 0);
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if (get_tmr_ms() > timeout)
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break;
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}
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return _sdmmc_storage_check_card_status(resp);
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}
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int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf)
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{
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// Request health report.
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if (!sdmmc_storage_execute_vendor_cmd(storage, MMC_SANDISK_HEALTH_REPORT))
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return 2;
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u32 tmp = 0;
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sdmmc_cmd_t cmdbuf;
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sdmmc_req_t reqbuf;
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sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_63_CMD, 0, SDMMC_RSP_TYPE_1, 0); // similar to CMD17 with arg 0x0.
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reqbuf.buf = buf;
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reqbuf.num_sectors = 1;
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reqbuf.blksize = 512;
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reqbuf.is_write = 0;
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reqbuf.is_multi_block = 0;
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reqbuf.is_auto_stop_trn = 0;
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u32 blkcnt_out;
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if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, &blkcnt_out))
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{
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sdmmc_stop_transmission(storage->sdmmc, &tmp);
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_sdmmc_storage_get_status(storage, &tmp, 0);
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return 0;
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}
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return 1;
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}
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static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out, u32 sector, u32 num_sectors, void *buf, u32 is_write)
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{
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u32 tmp = 0;
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@ -1360,8 +1414,6 @@ DPRINTF("[SD] SD does not support wide bus width\n");
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if (!_sd_storage_enable_uhs_low_volt(storage, type, buf))
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return 0;
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DPRINTF("[SD] enabled UHS\n");
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sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE);
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}
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else if (type != SDHCI_TIMING_SD_DS12 && storage->scr.sda_vsn) // Not default speed and not SD Version 1.0.
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{
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@ -1387,6 +1439,8 @@ DPRINTF("[SD] enabled HS\n");
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DPRINTF("[SD] got sd status\n");
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}
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sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE);
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storage->initialized = 1;
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return 1;
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@ -34,6 +34,81 @@ typedef enum _sdmmc_type
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EMMC_RPMB = 3
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} sdmmc_type;
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typedef struct _mmc_sandisk_advanced_report_t
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{
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u32 power_inits;
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u32 max_erase_cycles_sys;
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u32 max_erase_cycles_slc;
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u32 max_erase_cycles_mlc;
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u32 min_erase_cycles_sys;
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u32 min_erase_cycles_slc;
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u32 min_erase_cycles_mlc;
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u32 max_erase_cycles_euda;
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u32 min_erase_cycles_euda;
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u32 avg_erase_cycles_euda;
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u32 read_reclaim_cnt_euda;
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u32 bad_blocks_euda;
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u32 pre_eol_euda;
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u32 pre_eol_sys;
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u32 pre_eol_mlc;
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u32 uncorrectable_ecc;
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u32 temperature_now;
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u32 temperature_min;
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u32 temperature_max;
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u32 health_pct_euda;
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u32 health_pct_sys;
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u32 health_pct_mlc;
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u32 unk0;
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u32 unk1;
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u32 unk2;
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u32 reserved[78];
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} mmc_sandisk_advanced_report_t;
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typedef struct _mmc_sandisk_report_t
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{
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u32 avg_erase_cycles_sys;
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u32 avg_erase_cycles_slc;
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u32 avg_erase_cycles_mlc;
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u32 read_reclaim_cnt_sys;
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u32 read_reclaim_cnt_slc;
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u32 read_reclaim_cnt_mlc;
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u32 bad_blocks_factory;
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u32 bad_blocks_sys;
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u32 bad_blocks_slc;
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u32 bad_blocks_mlc;
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u32 fw_updates_cnt;
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u8 fw_update_date[12];
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u8 fw_update_time[8];
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u32 total_writes_100mb;
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u32 vdrops;
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u32 vdroops;
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u32 vdrops_failed_data_rec;
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u32 vdrops_data_rec_ops;
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u32 total_writes_slc_100mb;
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u32 total_writes_mlc_100mb;
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u32 mlc_bigfile_mode_limit_exceeded;
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u32 avg_erase_cycles_hybrid;
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mmc_sandisk_advanced_report_t advanced;
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} mmc_sandisk_report_t;
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typedef struct _mmc_cid
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{
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u32 manfid;
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@ -131,6 +206,9 @@ void sdmmc_storage_init_wait_sd();
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int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type);
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int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
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int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg);
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int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf);
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int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf);
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u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage);
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