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sdram: Update names for Aula
This commit is contained in:
parent
83ab79c51e
commit
f4696da0ef
6 changed files with 38 additions and 37 deletions
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@ -129,6 +129,7 @@ void minerva_change_freq(minerva_freq_t freq)
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if (!minerva_cfg)
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return;
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// Check if requested frequency is different. Do not allow otherwise because it will hang.
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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if (mtc_cfg->rate_from != freq)
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{
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@ -1430,12 +1430,12 @@ void *sdram_get_params_t210b01()
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case LPDDR4X_HOAG_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y:
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case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y:
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case LPDDR4X_SDS_4GB_SAMSUNG_1Y_A:
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case LPDDR4X_SDS_8GB_SAMSUNG_1Y_X:
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case LPDDR4X_SDS_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_AULA_4GB_SAMSUNG_1Y_A:
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case LPDDR4X_AULA_8GB_SAMSUNG_1Y_X:
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case LPDDR4X_AULA_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_IOWA_4GB_MICRON_1Y_A:
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case LPDDR4X_HOAG_4GB_MICRON_1Y_A:
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case LPDDR4X_SDS_4GB_MICRON_1Y_A:
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case LPDDR4X_AULA_4GB_MICRON_1Y_A:
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_sdram_patch_model_params_t210b01(dramid, (u32 *)buf);
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break;
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}
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@ -45,7 +45,7 @@ enum sdram_ids_erista
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LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0,
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LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1,
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LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2,
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LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3,
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LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to AULA Hynix 4GB 1Y-A.
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LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4,
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LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5,
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LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6,
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@ -76,14 +76,14 @@ enum sdram_ids_mariko
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LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y = 20,
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LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y = 21,
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LPDDR4X_SDS_4GB_SAMSUNG_1Y_A = 22,
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LPDDR4X_AULA_4GB_SAMSUNG_1Y_A = 22,
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LPDDR4X_SDS_8GB_SAMSUNG_1Y_X = 23,
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LPDDR4X_SDS_4GB_SAMSUNG_1Y_X = 24,
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LPDDR4X_AULA_8GB_SAMSUNG_1Y_X = 23,
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LPDDR4X_AULA_4GB_SAMSUNG_1Y_X = 24,
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LPDDR4X_IOWA_4GB_MICRON_1Y_A = 25,
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LPDDR4X_HOAG_4GB_MICRON_1Y_A = 26,
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LPDDR4X_SDS_4GB_MICRON_1Y_A = 27
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LPDDR4X_AULA_4GB_MICRON_1Y_A = 27
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};
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void sdram_init();
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@ -97,7 +97,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
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* DRAM size information
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* Specifies the value for EMC_ADR_CFG
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*/
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.emc_adr_cfg = 0x00000001, // 2 populated DRAM Devices.
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.emc_adr_cfg = 0x00000001, // 2 Ranks.
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/*
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* Specifies the time to wait after asserting pin
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@ -243,7 +243,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
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.emc_cfg_dig_dll = 0x002C00A0,
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.emc_cfg_dig_dll_1 = 0x00003701,
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.emc_cfg_dig_dll_period = 0x00008000,
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.emc_dev_select = 0x00000000, // Both devices.
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.emc_dev_select = 0x00000000, // Both Ranks.
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.emc_sel_dpd_ctrl = 0x00040008,
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/* Pads trimmer delays */
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@ -406,7 +406,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
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.pmc_ddr_ctrl = 0x0007FF8B,
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.emc_acpd_control = 0x00000000,
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.emc_swizzle_rank0_byte0 = 0x76543201,
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.emc_swizzle_rank0_byte0 = 0x76543201, // Overridden to 0x76543201 by spare6/7.
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.emc_swizzle_rank0_byte1 = 0x65324710,
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.emc_swizzle_rank0_byte2 = 0x25763410,
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.emc_swizzle_rank0_byte3 = 0x25673401,
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@ -454,7 +454,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
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.emc_pmacro_data_rx_term_mode = 0x00000010,
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.emc_pmacro_cmd_rx_term_mode = 0x00003000,
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.emc_pmacro_data_pad_tx_ctrl = 0x02000111,
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.emc_pmacro_common_pad_tx_ctrl = 0x00000008,
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.emc_pmacro_common_pad_tx_ctrl = 0x00000008, // Overridden to 0x0000000A by spare4/5.
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.emc_pmacro_cmd_pad_tx_ctrl = 0x0A000000,
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.emc_cfg3 = 0x00000040,
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@ -490,9 +490,9 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
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.emc_pmacro_cmd_ctrl2 = 0x0A0A0A0A,
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/* DRAM size information */
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.mc_emem_adr_cfg = 0x00000001, // 2 populated DRAM Devices.
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.mc_emem_adr_cfg_dev0 = 0x00070302, // Density 512MB.
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.mc_emem_adr_cfg_dev1 = 0x00070302, // Density 512MB.
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.mc_emem_adr_cfg = 0x00000001, // 2 Ranks.
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.mc_emem_adr_cfg_dev0 = 0x00070302, // Rank 0 Density 512MB.
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.mc_emem_adr_cfg_dev1 = 0x00070302, // Rank 1 Density 512MB.
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.mc_emem_adr_cfg_channel_mask = 0xFFFF2400,
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.mc_emem_adr_cfg_bank_mask0 = 0x6E574400,
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.mc_emem_adr_cfg_bank_mask1 = 0x39722800,
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@ -653,8 +653,8 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
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{ 0x00000005, 368, DRAM_ID(1) | DRAM_ID(5) }, // mc_emem_arb_timing_r2w.
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// Samsung 6GB density config.
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{ 0x000C0302, 347, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB sub-partition density.
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{ 0x000C0302, 348, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB sub-partition density.
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{ 0x000C0302, 347, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB Rank 0 density.
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{ 0x000C0302, 348, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB Rank 1 density.
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{ 0x00001800, 353, DRAM_ID(4) }, // mc_emem_cfg. 6GB total density.
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#ifdef CONFIG_SDRAM_COPPER_SUPPORT
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@ -122,7 +122,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
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* DRAM size information
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* Specifies the value for EMC_ADR_CFG
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*/
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.emc_adr_cfg = 0x00000000, // 1 populated DRAM Device.
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.emc_adr_cfg = 0x00000000, // 1 Rank.
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/*
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* Specifies the time to wait after asserting pin
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@ -273,7 +273,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
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.emc_cfg_dig_dll = 0x002C00A0,
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.emc_cfg_dig_dll_1 = 0x000F3701,
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.emc_cfg_dig_dll_period = 0x00008000,
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.emc_dev_select = 0x00000002, // Dev0 only.
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.emc_dev_select = 0x00000002, // Rank 0 only.
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.emc_sel_dpd_ctrl = 0x0004000C,
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/* Pads trimmer delays */
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@ -543,9 +543,9 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
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.emc_pmacro_cmd_ctrl2 = 0x00000000,
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/* DRAM size information */
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.mc_emem_adr_cfg = 0x00000000, // 1 populated DRAM Device.
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.mc_emem_adr_cfg_dev0 = 0x00080302, // Density 1024MB.
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.mc_emem_adr_cfg_dev1 = 0x00080302, // Density 1024MB.
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.mc_emem_adr_cfg = 0x00000000, // 1 Rank.
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.mc_emem_adr_cfg_dev0 = 0x00080302, // Rank 0 Density 1024MB.
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.mc_emem_adr_cfg_dev1 = 0x00080302, // Rank 1 Density 1024MB.
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.mc_emem_adr_cfg_channel_mask = 0xFFFF2400,
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.mc_emem_adr_cfg_bank_mask0 = 0x6E574400,
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.mc_emem_adr_cfg_bank_mask1 = 0x39722800,
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@ -733,7 +733,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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// Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ for SDEV Iowa and Hoag.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_auto_cal_vref_sel0.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_adr_cfg. 2 Ranks.
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{ 0x00000006, 0x1CC / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_quse.
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{ 0x00000005, 0x1D0 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_quse_width.
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{ 0x00000003, 0x1DC / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_einput.
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@ -764,7 +764,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x40000001, 0x45C / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_zcal_init_dev1.
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{ 0x00000000, 0x594 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_pmacro_tx_pwrd4.
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{ 0x00001000, 0x598 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // emc_pmacro_tx_pwrd5.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // mc_emem_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // mc_emem_adr_cfg. 2 Ranks.
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{ 0x00002000, 0x64C / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // mc_emem_cfg. 8GB total density.
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{ 0x00000002, 0x680 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // mc_emem_arb_timing_r2r.
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{ 0x02020001, 0x694 / 4, DRAM_ID2(9) | DRAM_ID2(13) }, // mc_emem_arb_da_turns.
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@ -810,7 +810,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x2A800000, 0x6DC / 4, DRAM_ID2(16) }, // mc_video_protect_gpu_override0.
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{ 0x00000002, 0x6E0 / 4, DRAM_ID2(16) }, // mc_video_protect_gpu_override1.
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// Samsung LPDDR4X 4GB 10nm-class (1y) Die-X for Iowa, Hoag and SDS.
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// Samsung LPDDR4X 4GB 10nm-class (1y) Die-X for Iowa, Hoag and Aula.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(17) | DRAM_ID2(19) | DRAM_ID2(24) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(17) | DRAM_ID2(19) | DRAM_ID2(24) }, // emc_auto_cal_vref_sel0.
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{ 0x00000006, 0x1CC / 4, DRAM_ID2(17) | DRAM_ID2(19) | DRAM_ID2(24) }, // emc_quse.
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@ -822,10 +822,10 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x2A800000, 0x6DC / 4, DRAM_ID2(17) | DRAM_ID2(19) | DRAM_ID2(24) }, // mc_video_protect_gpu_override0.
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{ 0x00000002, 0x6E0 / 4, DRAM_ID2(17) | DRAM_ID2(19) | DRAM_ID2(24) }, // mc_video_protect_gpu_override1.
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// Samsung LPDDR4X 8GB 10nm-class (1y) Die-X for SDEV Iowa and SDS.
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// Samsung LPDDR4X 8GB 10nm-class (1y) Die-X for SDEV Iowa and Aula.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_auto_cal_vref_sel0.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_adr_cfg. 2 Ranks.
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{ 0x00000006, 0x1CC / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_quse.
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{ 0x00000005, 0x1D0 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_quse_width.
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{ 0x00000003, 0x1DC / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_einput.
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@ -847,7 +847,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x40000001, 0x45C / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_zcal_init_dev1.
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{ 0x00000000, 0x594 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_pmacro_tx_pwrd4.
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{ 0x00001000, 0x598 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // emc_pmacro_tx_pwrd5.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // mc_emem_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // mc_emem_adr_cfg. 2 Ranks.
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{ 0x00002000, 0x64C / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // mc_emem_cfg. 8GB total density.
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{ 0x00000001, 0x670 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // mc_emem_arb_timing_faw.
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{ 0x00000002, 0x680 / 4, DRAM_ID2(18) | DRAM_ID2(23) }, // mc_emem_arb_timing_r2r.
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@ -881,7 +881,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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// Samsung LPDDR4X 8GB 10nm-class (1y) Die-Y for SDEV Iowa.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(21) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(21) }, // emc_auto_cal_vref_sel0.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(21) }, // emc_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x134 / 4, DRAM_ID2(21) }, // emc_adr_cfg. 2 Ranks.
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{ 0x00000008, 0x24C / 4, DRAM_ID2(21) }, // emc_tfaw.
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{ 0x08010004, 0x2B8 / 4, DRAM_ID2(21) }, // emc_mrw1.
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{ 0x08020000, 0x2BC / 4, DRAM_ID2(21) }, // emc_mrw2.
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@ -914,7 +914,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x40000001, 0x45C / 4, DRAM_ID2(21) }, // emc_zcal_init_dev1.
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{ 0x00000000, 0x594 / 4, DRAM_ID2(21) }, // emc_pmacro_tx_pwrd4.
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{ 0x00001000, 0x598 / 4, DRAM_ID2(21) }, // emc_pmacro_tx_pwrd5.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(21) }, // mc_emem_adr_cfg. 2 populated DRAM Devices.
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{ 0x00000001, 0x630 / 4, DRAM_ID2(21) }, // mc_emem_adr_cfg. 2 Ranks.
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{ 0x00002000, 0x64C / 4, DRAM_ID2(21) }, // mc_emem_cfg. 8GB total density.
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{ 0x00000001, 0x670 / 4, DRAM_ID2(21) }, // mc_emem_arb_timing_faw.
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{ 0x00000002, 0x680 / 4, DRAM_ID2(21) }, // mc_emem_arb_timing_r2r.
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@ -922,7 +922,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x2A800000, 0x6DC / 4, DRAM_ID2(21) }, // mc_video_protect_gpu_override0.
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{ 0x00000002, 0x6E0 / 4, DRAM_ID2(21) }, // mc_video_protect_gpu_override1.
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// Samsung LPDDR4X 4GB 10nm-class (1y) Die-A for Unknown SDS.
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// Samsung LPDDR4X 4GB 10nm-class (1y) Die-A for Unknown Aula.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(22) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(22) }, // emc_auto_cal_vref_sel0.
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{ 0x00000008, 0x24C / 4, DRAM_ID2(22) }, // emc_tfaw.
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@ -986,7 +986,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
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{ 0x00000002, 0x6E0 / 4, DRAM_ID2(22) }, // mc_video_protect_gpu_override1.
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{ 0x0000009C, 0x814 / 4, DRAM_ID2(22) }, // swizzle_rank_byte_encode.
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// Micron LPDDR4X 4GB 10nm-class (1y) Die-A for Unknown Iowa/Hoag/SDS.
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// Micron LPDDR4X 4GB 10nm-class (1y) Die-A for Unknown Iowa/Hoag/Aula.
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{ 0x05500000, 0x0D4 / 4, DRAM_ID2(25) | DRAM_ID2(26) | DRAM_ID2(27) }, // emc_auto_cal_config2.
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{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_ID2(25) | DRAM_ID2(26) | DRAM_ID2(27) }, // emc_auto_cal_vref_sel0.
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{ 0x00000006, 0x1CC / 4, DRAM_ID2(25) | DRAM_ID2(26) | DRAM_ID2(27) }, // emc_quse.
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@ -635,11 +635,11 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
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break;
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case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_X:
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case LPDDR4X_HOAG_4GB_SAMSUNG_1Y_X:
|
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case LPDDR4X_SDS_4GB_SAMSUNG_1Y_X:
|
||||
case LPDDR4X_AULA_4GB_SAMSUNG_1Y_X:
|
||||
strcpy(dram_man, "Samsung 1y X 4GB");
|
||||
break;
|
||||
case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_X:
|
||||
case LPDDR4X_SDS_8GB_SAMSUNG_1Y_X:
|
||||
case LPDDR4X_AULA_8GB_SAMSUNG_1Y_X:
|
||||
strcpy(dram_man, "Samsung 1y X 8GB");
|
||||
break;
|
||||
case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y:
|
||||
|
@ -648,12 +648,12 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
|
|||
case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y:
|
||||
strcpy(dram_man, "Samsung 1y Y 8GB");
|
||||
break;
|
||||
case LPDDR4X_SDS_4GB_SAMSUNG_1Y_A:
|
||||
case LPDDR4X_AULA_4GB_SAMSUNG_1Y_A:
|
||||
strcpy(dram_man, "Samsung 1y A 4GB");
|
||||
break;
|
||||
case LPDDR4X_IOWA_4GB_MICRON_1Y_A:
|
||||
case LPDDR4X_HOAG_4GB_MICRON_1Y_A:
|
||||
case LPDDR4X_SDS_4GB_MICRON_1Y_A:
|
||||
case LPDDR4X_AULA_4GB_MICRON_1Y_A:
|
||||
strcpy(dram_man, "Micron 1y A 4GB");
|
||||
break;
|
||||
default:
|
||||
|
|
Loading…
Reference in a new issue