CTCaer
90060d1d83
mtc: Don't rely on clean BSS for Minerva lib
2019-12-16 22:06:13 +02:00
CTCaer
e4f7928513
minerva: Fix compatibility check for hekate main
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Init now also returns status.
2019-12-09 22:27:01 +02:00
CTCaer
bd8a5ece58
heap: Fix type for heap monitor memset size
2019-12-09 19:30:45 +02:00
CTCaer
f256bd5909
Move all I/DRAM addresses into a memory map
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Many addresses were moved around to pack the memory usage!
2019-12-08 02:23:03 +02:00
CTCaer
6734513d47
Add missing dependencies for 2 previous commits
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- hos/mtc: Add FSP WAR and boost HOS booting times
- autoboot: Support VOL-+ combo for fastboot
2019-12-08 01:15:35 +02:00
CTCaer
84328aa676
minerva: Make use of new minerva
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- Training and switch is now faster
- Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva
- MTC table is now in a safe region
- Periodic training period increased to every 250ms
2019-12-04 21:56:45 +02:00
CTCaer
0b1eebefe1
Small refactor and bugfixes
2019-12-04 21:31:39 +02:00
CTCaer
ec10b572d1
heap: Quality updates to heap management
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- Allow reuse of unused sections that fit exactly to selected allocation size. Decreases fragmentation dramatically.
- Always allocate and align mapped memory to selected alignment. Avoids having fragmented unused maps that are not aligned.
- Use a static alignment based on BPMP and generally average cache line size. Boosts performance when MMU is used.
2019-12-04 19:02:28 +02:00
CTCaer
d1e50c558e
sdram: Refactor and fix some bugs in init
2019-12-04 18:53:36 +02:00
shchmue
426c86182d
heap: Prevent node chain collapse on free
2019-10-25 11:20:38 -06:00
Kostas Missos
7c42f72b8a
refactor: Remove all unwanted whitespace
2019-10-18 18:02:06 +03:00
CTCaer
95a6f2b763
sdram: Support fully burnt ODM fuses
2019-09-12 23:21:12 +03:00
CTCaer
a8d529cf6a
Refactoring and comment adding
2019-09-12 23:08:38 +03:00
Kostas Missos
718e502983
Add more register names + refactoring
2019-09-09 16:56:37 +03:00
CTCaer
f3d071ca69
mem: Remove memalign
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It doesn't do what it should anyway.
2019-08-28 02:08:12 +03:00
ctcaer@gmail.com
52478833de
[MTC] Utilize Minerva Training Cell
2019-06-30 03:49:33 +03:00
Kostas Missos
0ddc1c71a8
Bugfixes and hardcoded naming
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- Make debugmode for exosphere mandatory
- Support dev RSA modulus for warmboot
- Fix a critical bug where it allowed free() to be used on a non-heap address.
- Better the makefile
2019-03-08 00:19:04 +02:00
Kostas Missos
ec890c7c97
[PMIC] Refactoring
2019-02-16 01:23:14 +02:00
Kostas Missos
2f37811aba
Normalize brom patches & add sd autocalib fallback
2019-02-12 00:40:40 +02:00
Kostas Missos
4ae42c3a9d
Small fixes and whitespace
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Additionally make info functions smaller and show available fuses.
2019-02-12 00:34:35 +02:00
Kostas Missos
e105634b0d
Proper warmboot exploit impl and documentation
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Side effect:
Fixed a bug where the dumped patched bootrom had the warmboot exploit patch
Co-Authored-By: Balázs Triszka <balika011@gmail.com>
2018-12-17 21:10:13 +02:00
balika011
8b8f3c564c
Fine-tune dram configs
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Helps overclocking
2018-12-16 14:51:16 +01:00
Kostas Missos
267a04c4ac
Fix HDCP + some bugfixes
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Thanks @hexkyz for taking the time to recheck for the missing 6.x changes
2018-11-20 21:32:54 +02:00
Kostas Missos
4eb5b5f91b
Name more hardcoded regs/vals
2018-11-10 14:11:42 +02:00
Kostas Missos
fdd94ffd2b
General bugfixes + hardcoded name replacement
2018-09-18 23:38:54 +03:00
Kostas Missos
6b8887b5d8
Move display_end before secmon + add boolean supp.
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Currently bpmp loses access to the relevant registers when secmon or exosphere is launched.
This change provides support for all firmwares and properly sanitizes the display.
2018-08-13 12:12:53 +03:00
Kostas Missos
e5abdd938e
Refactor ALL the things + enable LTO
2018-08-13 11:58:24 +03:00
