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hekate/modules/hekate_libsys_minerva
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CTCaer 07d1982abf minerva: add compile time sdram voltage change
2021-04-11 10:31:57 +03:00
..
Makefile Add proper make prints for modules 2020-07-18 01:36:16 +03:00
mtc.h minerva: more accurate clock tree delays 2021-04-11 09:50:06 +03:00
mtc_mc_emc_regs.h minerva: Update to v1.2 and use only integers 2019-12-04 21:46:33 +02:00
mtc_switch_tables.h mtc: Name sdram ids 2020-06-14 17:39:39 +03:00
mtc_table.h mtc: Refactor various types 2021-01-03 14:33:56 +02:00
README.md refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
sys_sdrammtc.c minerva: add compile time sdram voltage change 2021-04-11 10:31:57 +03:00
types.h Minerva our DRAM trainer 2018-11-04 03:15:32 +02:00

README.md

Minerva Training Cell

Custom Nvidia Tegra X1 DRAM trainer.

For more, check Here.

Minerva Training Cell (c) 2018 CTCaer.

/* Pain... And suffering. */