mirror of
https://github.com/CTCaer/hekate.git
synced 2024-09-19 21:44:57 +01:00
9e41aa7759
- Allow ASID to be configured - Allow 34-bit PAs - Use special type for setting PDE/PTE config - Initialize all pages as non accessible - Add function for mapping 4MB regions directly - Add SMMU heap reset function - Correct address load OP to 32-bit and remove alignment on SMMU enable payload - Refactor all defines
246 lines
6.1 KiB
C
246 lines
6.1 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 balika011
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <soc/bpmp.h>
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#include <soc/ccplex.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <mem/mc_t210.h>
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#include <mem/smmu.h>
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#include <memory_map.h>
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/*! SMMU register defines */
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#define SMMU_ASID(asid) (((asid) << 24u) | ((asid) << 16u) | ((asid) << 8u) | (asid))
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#define SMMU_ENABLE BIT(31)
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#define SMMU_TLB_ACTIVE_LINES(l) ((l) << 0u)
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#define SMMU_TLB_RR_ARBITRATION BIT(28)
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#define SMMU_TLB_HIT_UNDER_MISS BIT(29)
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#define SMMU_TLB_STATS_ENABLE BIT(31)
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#define SMUU_PTC_INDEX_MAP(m) ((m) << 0u)
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#define SMUU_PTC_LINE_MASK(m) ((m) << 8u)
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#define SMUU_PTC_REQ_LIMIT(l) ((l) << 24u)
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#define SMUU_PTC_CACHE_ENABLE BIT(29)
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#define SMUU_PTC_STATS_ENABLE BIT(31)
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/*! Page table defines */
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#define SMMU_4MB_REGION 0
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#define SMMU_PAGE_TABLE 1
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PAGE_SHIFT 12u
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#define SMMU_PTN_SHIFT SMMU_PAGE_SHIFT
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#define SMMU_PDN_SHIFT 22u
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> SMMU_PAGE_SHIFT)
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#define SMMU_ADDR_TO_PTN(addr) ((addr) >> SMMU_PTN_SHIFT)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> SMMU_PDN_SHIFT)
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#define SMMU_PTN_TO_ADDR(ptn) ((ptn) << SMMU_PTN_SHIFT)
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#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << SMMU_PDN_SHIFT)
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#define SMMU_PTB(page, attr) (((attr) << 29u) | ((page) >> SMMU_PAGE_SHIFT))
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static void *smmu_heap = (void *)SMMU_HEAP_ADDR;
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// Enabling SMMU requires a TZ (EL3) secure write. MC(MC_SMMU_CONFIG) = 1;
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static const u8 smmu_enable_payload[] = {
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0xC1, 0x00, 0x00, 0x18, // 0x00: LDR W1, =0x70019010
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0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
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0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
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0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
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0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
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0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
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0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
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};
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void *smmu_page_zalloc(u32 num)
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{
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void *page = smmu_heap;
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memset(page, 0, SZ_PAGE * num);
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smmu_heap += SZ_PAGE * num;
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return page;
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}
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static pde_t *_smmu_pdir_alloc()
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{
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pde_t *pdir = (pde_t *)smmu_page_zalloc(1);
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// Initialize pdes with no permissions.
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for (u32 pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn].huge.page = pdn;
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return pdir;
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}
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static void _smmu_flush_regs()
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{
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(void)MC(MC_SMMU_PTB_DATA);
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}
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void smmu_flush_all()
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{
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// Flush the entire page table cache.
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MC(MC_SMMU_PTC_FLUSH) = 0;
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_smmu_flush_regs();
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// Flush the entire table.
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MC(MC_SMMU_TLB_FLUSH) = 0;
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_smmu_flush_regs();
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}
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void smmu_init()
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{
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MC(MC_SMMU_PTB_ASID) = 0;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TLB_CONFIG) = SMMU_TLB_HIT_UNDER_MISS | SMMU_TLB_RR_ARBITRATION | SMMU_TLB_ACTIVE_LINES(48);
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MC(MC_SMMU_PTC_CONFIG) = SMUU_PTC_CACHE_ENABLE | SMUU_PTC_REQ_LIMIT(8) | SMUU_PTC_LINE_MASK(0xF) | SMUU_PTC_INDEX_MAP(0x3F);
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MC(MC_SMMU_PTC_FLUSH) = 0;
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MC(MC_SMMU_TLB_FLUSH) = 0;
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}
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void smmu_enable()
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{
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static bool enabled = false;
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if (enabled)
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return;
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// Launch payload on CCPLEX in order to set SMMU enable bit.
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ccplex_boot_cpu0((u32)smmu_enable_payload, false);
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msleep(100);
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ccplex_powergate_cpu0();
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smmu_flush_all();
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enabled = true;
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}
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void smmu_reset_heap()
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{
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smmu_heap = (void *)SMMU_HEAP_ADDR;
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}
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void *smmu_init_domain(u32 dev_base, u32 asid)
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{
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void *ptb = _smmu_pdir_alloc();
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = SMMU_PTB((u32)ptb, SMMU_ATTR_ALL);
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_smmu_flush_regs();
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// Use the same macro for both quad and single domains. Reserved bits are not set anyway.
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MC(dev_base) = SMMU_ENABLE | SMMU_ASID(asid);
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_smmu_flush_regs();
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return ptb;
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}
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void smmu_deinit_domain(u32 dev_base, u32 asid)
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{
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(dev_base) = 0;
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_smmu_flush_regs();
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}
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void smmu_domain_bypass(u32 dev_base, bool bypass)
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{
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if (bypass)
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{
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smmu_flush_all();
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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MC(dev_base) &= ~SMMU_ENABLE;
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}
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else
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{
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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MC(dev_base) |= SMMU_ENABLE;
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smmu_flush_all();
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}
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_smmu_flush_regs();
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}
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static pte_t *_smmu_get_pte(pde_t *pdir, u32 iova)
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{
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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pte_t *ptbl;
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// Get 4MB page table or initialize one.
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if (pdir[pdn].tbl.attr)
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ptbl = (pte_t *)(SMMU_PTN_TO_ADDR(pdir[pdn].tbl.table));
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else
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{
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// Allocate page table.
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ptbl = (pte_t *)smmu_page_zalloc(1);
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// Get address.
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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// Initialize page table with no permissions.
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for (u32 pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SZ_PAGE)
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ptbl[pn].page = SMMU_ADDR_TO_PFN(addr);
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// Set page table to the page directory.
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pdir[pdn].tbl.table = SMMU_ADDR_TO_PTN((u32)ptbl);
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pdir[pdn].tbl.next = SMMU_PAGE_TABLE;
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pdir[pdn].tbl.attr = SMMU_ATTR_ALL;
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smmu_flush_all();
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}
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return &ptbl[SMMU_ADDR_TO_PTN(iova) % SMMU_PTBL_COUNT];
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}
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void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr)
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{
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// Map pages to page table entries. VA/PA should be aligned to 4KB.
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for (u32 i = 0; i < pages; i++)
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{
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pte_t *pte = _smmu_get_pte((pde_t *)ptb, iova);
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pte->page = SMMU_ADDR_TO_PFN(iopa);
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pte->attr = attr;
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iova += SZ_PAGE;
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iopa += SZ_PAGE;
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}
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smmu_flush_all();
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}
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void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr)
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{
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pde_t *pdir = (pde_t *)ptb;
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// Map 4MB regions to page directory entries. VA/PA should be aligned to 4MB.
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for (u32 i = 0; i < regions; i++)
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{
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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pdir[pdn].huge.page = SMMU_ADDR_TO_PDN(iopa);
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pdir[pdn].huge.next = SMMU_4MB_REGION;
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pdir[pdn].huge.attr = attr;
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iova += SZ_4M;
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iopa += SZ_4M;
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}
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smmu_flush_all();
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}
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