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hekate/modules/hekate_libsys_minerva
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CTCaer 418f029d11 lib: minerva: add 1966 and 2033 MHz in div table
2023-06-08 05:31:15 +03:00
..
Makefile
mtc.h
mtc_mc_emc_regs.h
mtc_switch_tables.h
mtc_table.h
README.md
sys_sdrammtc.c
types.h

README.md

Minerva Training Cell

Custom Nvidia Tegra X1 DRAM trainer.

For more, check Here.

Minerva Training Cell (c) 2018 CTCaer.

/* Pain... And suffering. */