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https://github.com/CTCaer/hekate.git
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0b45a5a11a
3 users had issues with 602MHz. This will probably bring the SoC binning compatibility to 100%. Additionally, make it easy to change default boost frequency. The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BPMP_H_
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#define _BPMP_H_
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#include "../utils/types.h"
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#define BPMP_MMU_MAINT_CLEAN_WAY 17
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#define BPMP_MMU_MAINT_INVALID_WAY 18
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#define BPMP_MMU_MAINT_CLN_INV_WAY 19
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typedef struct _bpmp_mmu_entry_t
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{
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u32 min_addr;
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u32 max_addr;
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u32 attr;
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u32 enable;
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} bpmp_mmu_entry_t;
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typedef enum
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{
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BPMP_CLK_NORMAL, // 408MHz 0% - 136MHz APB.
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BPMP_CLK_HIGH_BOOST, // 544MHz 33% - 136MHz APB.
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BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
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BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
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//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
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BPMP_CLK_MAX
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} bpmp_freq_t;
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#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
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void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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void bpmp_clk_rate_set(bpmp_freq_t fid);
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void bpmp_usleep(u32 us);
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void bpmp_msleep(u32 ms);
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void bpmp_halt();
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#endif
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