mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-23 16:36:03 +00:00
296 lines
12 KiB
C
296 lines
12 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 shuffle2
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* Copyright (c) 2018 balika011
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* Copyright (c) 2019-2023 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _FUSE_H_
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#define _FUSE_H_
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#include <utils/types.h>
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/*! Fuse registers. */
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#define FUSE_CTRL 0x0
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#define FUSE_ADDR 0x4
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#define FUSE_RDATA 0x8
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#define FUSE_WDATA 0xC
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#define FUSE_TIME_RD1 0x10
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#define FUSE_TIME_RD2 0x14
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#define FUSE_TIME_PGM1 0x18
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#define FUSE_TIME_PGM2 0x1C
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#define FUSE_PRIV2INTFC 0x20
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#define FUSE_FUSEBYPASS 0x24
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#define FUSE_PRIVATEKEYDISABLE 0x28
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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#define FUSE_PRIV2RESHIFT 0x3C
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#define FUSE_FUSETIME_RD0 0x40
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#define FUSE_FUSETIME_RD1 0x44
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#define FUSE_FUSETIME_RD2 0x48
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#define FUSE_FUSETIME_RD3 0x4C
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#define FUSE_PRIVATE_KEY0_NONZERO 0x80
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#define FUSE_PRIVATE_KEY1_NONZERO 0x84
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#define FUSE_PRIVATE_KEY2_NONZERO 0x88
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#define FUSE_PRIVATE_KEY3_NONZERO 0x8C
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#define FUSE_PRIVATE_KEY4_NONZERO 0x90
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/*! Fuse Cached registers */
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#define FUSE_RESERVED_ODM8_B01 0x98
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#define FUSE_RESERVED_ODM9_B01 0x9C
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#define FUSE_RESERVED_ODM10_B01 0xA0
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#define FUSE_RESERVED_ODM11_B01 0xA4
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#define FUSE_RESERVED_ODM12_B01 0xA8
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#define FUSE_RESERVED_ODM13_B01 0xAC
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#define FUSE_RESERVED_ODM14_B01 0xB0
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#define FUSE_RESERVED_ODM15_B01 0xB4
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#define FUSE_RESERVED_ODM16_B01 0xB8
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#define FUSE_RESERVED_ODM17_B01 0xBC
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#define FUSE_RESERVED_ODM18_B01 0xC0
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#define FUSE_RESERVED_ODM19_B01 0xC4
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#define FUSE_RESERVED_ODM20_B01 0xC8
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#define FUSE_RESERVED_ODM21_B01 0xCC
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#define FUSE_KEK00_B01 0xD0
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#define FUSE_KEK01_B01 0xD4
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#define FUSE_KEK02_B01 0xD8
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#define FUSE_KEK03_B01 0xDC
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#define FUSE_BEK00_B01 0xE0
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#define FUSE_BEK01_B01 0xE4
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#define FUSE_BEK02_B01 0xE8
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#define FUSE_BEK03_B01 0xEC
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#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0
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#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4
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#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4SVT_B01 0xF8
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#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4SVT_B01 0xFC
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#define FUSE_PRODUCTION_MODE 0x100
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#define FUSE_JTAG_SECUREID_VALID 0x104
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#define FUSE_ODM_LOCK 0x108
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#define FUSE_OPT_OPENGL_EN 0x10C
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#define FUSE_SKU_INFO 0x110
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#define FUSE_CPU_SPEEDO_0_CALIB 0x114
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#define FUSE_CPU_IDDQ_CALIB 0x118
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#define FUSE_RESERVED_ODM22_B01 0x11C
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#define FUSE_RESERVED_ODM23_B01 0x120
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#define FUSE_RESERVED_ODM24_B01 0x124
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#define FUSE_OPT_FT_REV 0x128
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#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
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#define FUSE_CPU_SPEEDO_2_CALIB 0x130
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#define FUSE_SOC_SPEEDO_0_CALIB 0x134
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#define FUSE_SOC_SPEEDO_1_CALIB 0x138
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#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
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#define FUSE_SOC_IDDQ_CALIB 0x140
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#define FUSE_RESERVED_ODM25_B01 0x144
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#define FUSE_FA 0x148
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#define FUSE_RESERVED_PRODUCTION 0x14C
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#define FUSE_HDMI_LANE0_CALIB 0x150
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#define FUSE_HDMI_LANE1_CALIB 0x154
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#define FUSE_HDMI_LANE2_CALIB 0x158
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#define FUSE_HDMI_LANE3_CALIB 0x15C
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#define FUSE_ENCRYPTION_RATE 0x160
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#define FUSE_PUBLIC_KEY0 0x164
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#define FUSE_PUBLIC_KEY1 0x168
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#define FUSE_PUBLIC_KEY2 0x16C
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#define FUSE_PUBLIC_KEY3 0x170
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#define FUSE_PUBLIC_KEY4 0x174
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#define FUSE_PUBLIC_KEY5 0x178
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#define FUSE_PUBLIC_KEY6 0x17C
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#define FUSE_PUBLIC_KEY7 0x180
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#define FUSE_TSENSOR1_CALIB 0x184
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#define FUSE_TSENSOR2_CALIB 0x188
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#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
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#define FUSE_OPT_CP_REV 0x190
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#define FUSE_OPT_PFG 0x194
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#define FUSE_TSENSOR0_CALIB 0x198
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
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#define FUSE_SECURITY_MODE 0x1A0
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#define FUSE_PRIVATE_KEY0 0x1A4
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#define FUSE_PRIVATE_KEY1 0x1A8
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#define FUSE_PRIVATE_KEY2 0x1AC
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_ARM_JTAG_DIS 0x1B8
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#define FUSE_BOOT_DEVICE_INFO 0x1BC
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_OPT_VP9_DISABLE 0x1C4
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#define FUSE_RESERVED_ODM0 0x1C8
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#define FUSE_RESERVED_ODM1 0x1CC
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#define FUSE_RESERVED_ODM2 0x1D0
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#define FUSE_RESERVED_ODM3 0x1D4
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#define FUSE_RESERVED_ODM4 0x1D8
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#define FUSE_RESERVED_ODM5 0x1DC
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#define FUSE_RESERVED_ODM6 0x1E0
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#define FUSE_RESERVED_ODM7 0x1E4
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#define FUSE_OBS_DIS 0x1E8
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#define FUSE_OPT_NVJTAG_PROTECTION_ENABLE_B01 0x1EC
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8
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#define FUSE_PACKAGE_INFO 0x1FC
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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#define FUSE_OPT_LOT_CODE_0 0x208
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#define FUSE_OPT_LOT_CODE_1 0x20C
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#define FUSE_OPT_WAFER_ID 0x210
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_OPT_SEC_DEBUG_EN 0x21C
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#define FUSE_OPT_OPS_RESERVED 0x220
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#define FUSE_SATA_CALIB 0x224
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#define FUSE_SPARE_REGISTER_ODM_B01 0x224
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_TSENSOR3_CALIB 0x22C
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#define FUSE_CLOCK_BONDOUT0 0x230
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#define FUSE_CLOCK_BONDOUT1 0x234
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#define FUSE_RESERVED_ODM26_B01 0x238
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#define FUSE_RESERVED_ODM27_B01 0x23C
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#define FUSE_RESERVED_ODM28_B01 0x240
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#define FUSE_OPT_SAMPLE_TYPE 0x244
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#define FUSE_OPT_SUBREVISION 0x248
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#define FUSE_OPT_SW_RESERVED_0 0x24C
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#define FUSE_OPT_SW_RESERVED_1 0x250
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#define FUSE_TSENSOR4_CALIB 0x254
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#define FUSE_TSENSOR5_CALIB 0x258
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#define FUSE_TSENSOR6_CALIB 0x25C
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#define FUSE_TSENSOR7_CALIB 0x260
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#define FUSE_OPT_PRIV_SEC_DIS 0x264
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#define FUSE_PKC_DISABLE 0x268
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#define FUSE_BOOT_SECURITY_INFO_B01 0x268
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#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C
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#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270
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#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4HVT_B01 0x274
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#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4HVT_B01 0x278
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#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C
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#define FUSE_TSENSOR_COMMON 0x280
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#define FUSE_OPT_CP_BIN 0x284
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#define FUSE_OPT_GPU_DISABLE 0x288
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#define FUSE_OPT_FT_BIN 0x28C
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#define FUSE_OPT_DONE_MAP 0x290
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#define FUSE_RESERVED_ODM29_B01 0x294
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#define FUSE_APB2JTAG_DISABLE 0x298
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#define FUSE_ODM_INFO 0x29C
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#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
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#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0
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#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4
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#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8
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#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC
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#define FUSE_WOA_SKU_FLAG 0x2C0
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#define FUSE_ECO_RESERVE_1 0x2C4
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#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
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#define FUSE_PRODUCTION_MONTH 0x2CC
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#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
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#define FUSE_TSENSOR9_CALIB 0x2D4
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#define FUSE_VMIN_CALIBRATION 0x2DC
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#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
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#define FUSE_DEBUG_AUTHENTICATION 0x2E4
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#define FUSE_SECURE_PROVISION_INDEX 0x2E8
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#define FUSE_SECURE_PROVISION_INFO 0x2EC
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#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
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#define FUSE_SPARE_ENDIS 0x2F4
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#define FUSE_ECO_RESERVE_0 0x2F8
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#define FUSE_RESERVED_CALIB0 0x304
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#define FUSE_RESERVED_CALIB1 0x308
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#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
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#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
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#define FUSE_OPT_CPU_DISABLE 0x314
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#define FUSE_OPT_CPU_DISABLE_CP1 0x318
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#define FUSE_TSENSOR10_CALIB 0x31C
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#define FUSE_TSENSOR10_CALIB_AUX 0x320
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#define FUSE_OPT_RAM_SVOP_DP 0x324
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#define FUSE_OPT_RAM_SVOP_PDP 0x328
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#define FUSE_OPT_RAM_SVOP_REG 0x32C
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#define FUSE_OPT_RAM_SVOP_SP 0x330
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#define FUSE_OPT_RAM_SVOP_SMPDP 0x334
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#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4HVT_B01 0x324
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#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
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#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
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#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
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#define FUSE_OPT_ROM_SVOP_SP_B01 0x334
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#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
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#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
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#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340
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#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344
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#define FUSE_OPT_CPU_DISABLE_CP2 0x348
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#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
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#define FUSE_USB_CALIB_EXT 0x350
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#define FUSE_RESERVED_FIELD 0x354
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#define FUSE_SPARE_REALIGNMENT_REG 0x37C
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#define FUSE_SPARE_BIT_0 0x380
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//...
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#define FUSE_SPARE_BIT_31 0x3FC
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/*! Fuse commands. */
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#define FUSE_READ 0x1
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#define FUSE_WRITE 0x2
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#define FUSE_SENSE 0x3
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#define FUSE_CMD_MASK 0x3
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/*! Fuse cache registers. */
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#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
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#define FUSE_ARRAY_WORDS_NUM 192
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#define FUSE_ARRAY_WORDS_NUM_B01 256
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enum
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{
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FUSE_NX_HW_TYPE_ICOSA,
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FUSE_NX_HW_TYPE_IOWA,
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FUSE_NX_HW_TYPE_HOAG,
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FUSE_NX_HW_TYPE_AULA
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};
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enum
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{
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FUSE_NX_HW_STATE_PROD,
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FUSE_NX_HW_STATE_DEV
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};
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void fuse_disable_program();
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u32 fuse_read_odm(u32 idx);
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u32 fuse_read_odm_keygen_rev();
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u32 fuse_read_dramid(bool raw_id);
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u32 fuse_read_hw_state();
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u32 fuse_read_hw_type();
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int fuse_set_sbk();
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void fuse_wait_idle();
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int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
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int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
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void fuse_read_array(u32 *words);
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bool fuse_check_patched_rcm();
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#endif
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