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faf5651607
Additionally, do not restore source DPD ctrl when switching frequencies or training is not needed.
143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
/*
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* Minerva Training Cell
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* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
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*
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* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MTC_H_
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#define _MTC_H_
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#include "mtc_table.h"
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#include "types.h"
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/* Address bases and access macros - Change these for mapped access */
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define MTC_INIT_MAGIC 0x3043544D
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#define MTC_NEW_MAGIC 0x5243544D
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#define _REG(base, off) *(vu32 *)((base) + (off))
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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/* End of addresses and access macros */
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#define EMC_TABLE_SIZE_R7 49280
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#define EMC_TABLE_ENTRY_SIZE_R7 4928
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#define EMC_TABLE_ENTRY_SIZE_R3 4300
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#define EMC_STATUS_UPDATE_TIMEOUT 1000
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#define EMC_PERIODIC_TRAIN_MS 100
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#define EMC_TEMP_COMP_MS 1000
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typedef struct
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{
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s32 rate_to;
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s32 rate_from;
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emc_table_t *mtc_table;
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u32 table_entries;
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emc_table_t *current_emc_table;
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u32 train_mode;
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u32 sdram_id;
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u32 prev_temp;
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bool emc_2X_clk_src_is_pllmb;
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bool fsp_for_src_freq;
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bool train_ram_patterns;
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bool init_done;
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} mtc_config_t;
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enum train_mode_t
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{
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OP_SWITCH = 0,
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OP_TRAIN = 1,
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OP_TRAIN_SWITCH = 2,
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OP_PERIODIC_TRAIN = 3,
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OP_TEMP_COMP = 4
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};
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enum comp_seq_t
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{
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DVFS_SEQUENCE = 1,
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WRITE_TRAINING_SEQUENCE = 2,
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PERIODIC_TRAINING_SEQUENCE = 3
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};
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enum tree_update_mode_t
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{
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DVFS_PT1 = 10,
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DVFS_UPDATE = 11,
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TRAINING_PT1 = 12,
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TRAINING_UPDATE = 13,
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PERIODIC_TRAINING_UPDATE = 14
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};
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enum emc_channels
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{
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EMC_CH0 = 0,
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EMC_CH1 = 1
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};
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enum EMC_2X_CLK_SRC
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{
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PLLM_OUT0 = 0x0,
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PLLC_OUT0 = 0x1,
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PLLP_OUT0 = 0x2,
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CLK_M = 0x3,
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PLLM_UD = 0x4,
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PLLMB_UD = 0x5,
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PLLMB_OUT0 = 0x6,
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PLLP_UD = 0x7
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};
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enum DRAM_TYPE
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{
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DRAM_TYPE_DDR3 = 0,
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DRAM_TYPE_LPDDR4 = 1,
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DRAM_TYPE_LPDDR2 = 2,
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DRAM_TYPE_DDR2 = 3
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};
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enum DRAM_DEV_NO
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{
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ONE_RANK = 1,
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TWO_RANK = 2
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};
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enum DRAM_OVER_TEMP_REF
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{
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REFRESH_X2 = 1,
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REFRESH_X4 = 2
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};
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/* Timers for the below two compensation functions should be paused when changing timings. */
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/* Change refresh rate based on dram temps. Run every 1000ms. */
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/* Timer should be run only when another component reports over temperature. */
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void _minerva_do_over_temp_compensation(mtc_config_t *mtc_cfg);
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/* Periodic compensation only for tight timings that need it. Run every 100ms. */
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/* Over temp and periodic compensation, should not access EMC_MRR at the same time. */
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u32 _minerva_do_periodic_compensation(emc_table_t *mtc_table_entry);
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#endif
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