2014-04-09 00:19:26 +01:00
|
|
|
// Copyright 2014 Citra Emulator Project
|
2014-12-17 05:38:14 +00:00
|
|
|
// Licensed under GPLv2 or any later version
|
2014-11-19 08:49:13 +00:00
|
|
|
// Refer to the license.txt file included.
|
2014-04-05 03:26:06 +01:00
|
|
|
|
|
|
|
#pragma once
|
|
|
|
|
2018-01-09 21:33:46 +00:00
|
|
|
#include <array>
|
2014-04-09 01:15:08 +01:00
|
|
|
#include "common/common_types.h"
|
2018-12-19 03:10:51 +00:00
|
|
|
#include "common/logging/log.h"
|
|
|
|
#include "core/memory.h"
|
2018-09-21 00:28:48 +01:00
|
|
|
|
|
|
|
namespace Kernel {
|
|
|
|
enum class VMAPermission : u8;
|
|
|
|
}
|
2014-04-05 03:26:06 +01:00
|
|
|
|
2018-08-25 02:43:32 +01:00
|
|
|
namespace Core {
|
|
|
|
|
2018-09-18 07:49:40 +01:00
|
|
|
/// Generic ARMv8 CPU interface
|
2014-04-27 23:29:51 +01:00
|
|
|
class ARM_Interface : NonCopyable {
|
2014-04-05 03:26:06 +01:00
|
|
|
public:
|
2016-09-19 02:01:46 +01:00
|
|
|
virtual ~ARM_Interface() {}
|
2014-04-05 03:26:06 +01:00
|
|
|
|
2016-12-22 05:08:09 +00:00
|
|
|
struct ThreadContext {
|
2018-01-09 21:33:46 +00:00
|
|
|
std::array<u64, 31> cpu_registers;
|
2017-08-29 02:09:42 +01:00
|
|
|
u64 sp;
|
|
|
|
u64 pc;
|
2018-09-29 22:58:26 +01:00
|
|
|
u32 pstate;
|
|
|
|
std::array<u8, 4> padding;
|
2018-09-18 07:49:40 +01:00
|
|
|
std::array<u128, 32> vector_registers;
|
2018-09-29 22:58:26 +01:00
|
|
|
u32 fpcr;
|
|
|
|
u32 fpsr;
|
|
|
|
u64 tpidr;
|
2016-12-22 05:08:09 +00:00
|
|
|
};
|
2018-09-29 22:58:26 +01:00
|
|
|
// Internally within the kernel, it expects the AArch64 version of the
|
|
|
|
// thread context to be 800 bytes in size.
|
|
|
|
static_assert(sizeof(ThreadContext) == 0x320);
|
2016-12-22 05:08:09 +00:00
|
|
|
|
2018-02-14 17:47:48 +00:00
|
|
|
/// Runs the CPU until an event happens
|
|
|
|
virtual void Run() = 0;
|
2014-05-17 16:59:18 +01:00
|
|
|
|
2014-04-05 20:23:59 +01:00
|
|
|
/// Step CPU by one instruction
|
2018-02-14 17:47:48 +00:00
|
|
|
virtual void Step() = 0;
|
2014-05-17 16:59:18 +01:00
|
|
|
|
2018-03-16 22:22:14 +00:00
|
|
|
/// Maps a backing memory region for the CPU
|
2018-09-15 14:21:06 +01:00
|
|
|
virtual void MapBackingMemory(VAddr address, std::size_t size, u8* memory,
|
2018-03-16 22:22:14 +00:00
|
|
|
Kernel::VMAPermission perms) = 0;
|
|
|
|
|
|
|
|
/// Unmaps a region of memory that was previously mapped using MapBackingMemory
|
2018-09-15 14:21:06 +01:00
|
|
|
virtual void UnmapMemory(VAddr address, std::size_t size) = 0;
|
2017-10-10 04:56:20 +01:00
|
|
|
|
2016-06-27 19:38:49 +01:00
|
|
|
/// Clear all instruction cache
|
|
|
|
virtual void ClearInstructionCache() = 0;
|
|
|
|
|
2017-09-24 22:44:13 +01:00
|
|
|
/// Notify CPU emulation that page tables have changed
|
|
|
|
virtual void PageTableChanged() = 0;
|
|
|
|
|
2014-04-05 20:23:59 +01:00
|
|
|
/**
|
|
|
|
* Set the Program Counter to an address
|
|
|
|
* @param addr Address to set PC to
|
|
|
|
*/
|
2017-08-29 02:09:42 +01:00
|
|
|
virtual void SetPC(u64 addr) = 0;
|
2014-04-05 20:23:59 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the current Program Counter
|
|
|
|
* @return Returns current PC
|
|
|
|
*/
|
2017-08-29 02:09:42 +01:00
|
|
|
virtual u64 GetPC() const = 0;
|
2014-04-05 20:23:59 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Get an ARM register
|
2017-08-29 02:09:42 +01:00
|
|
|
* @param index Register index
|
2014-04-05 20:23:59 +01:00
|
|
|
* @return Returns the value in the register
|
|
|
|
*/
|
2017-08-29 02:09:42 +01:00
|
|
|
virtual u64 GetReg(int index) const = 0;
|
2014-04-05 20:23:59 +01:00
|
|
|
|
2014-04-11 00:57:56 +01:00
|
|
|
/**
|
|
|
|
* Set an ARM register
|
2017-08-29 02:09:42 +01:00
|
|
|
* @param index Register index
|
2014-04-11 00:57:56 +01:00
|
|
|
* @param value Value to set register to
|
|
|
|
*/
|
2017-08-29 02:09:42 +01:00
|
|
|
virtual void SetReg(int index, u64 value) = 0;
|
2014-04-11 00:57:56 +01:00
|
|
|
|
2015-08-07 02:24:25 +01:00
|
|
|
/**
|
2018-09-18 07:49:40 +01:00
|
|
|
* Gets the value of a specified vector register.
|
|
|
|
*
|
|
|
|
* @param index The index of the vector register.
|
|
|
|
* @return the value within the vector register.
|
2015-08-07 02:24:25 +01:00
|
|
|
*/
|
2018-09-18 07:49:40 +01:00
|
|
|
virtual u128 GetVectorReg(int index) const = 0;
|
2015-08-07 02:24:25 +01:00
|
|
|
|
|
|
|
/**
|
2018-09-18 07:49:40 +01:00
|
|
|
* Sets a given value into a vector register.
|
|
|
|
*
|
|
|
|
* @param index The index of the vector register.
|
|
|
|
* @param value The new value to place in the register.
|
2015-08-07 02:24:25 +01:00
|
|
|
*/
|
2018-09-18 07:49:40 +01:00
|
|
|
virtual void SetVectorReg(int index, u128 value) = 0;
|
2015-08-07 02:24:25 +01:00
|
|
|
|
2014-04-05 20:23:59 +01:00
|
|
|
/**
|
2018-09-18 07:49:40 +01:00
|
|
|
* Get the current PSTATE register
|
|
|
|
* @return Returns the value of the PSTATE register
|
2014-04-05 20:23:59 +01:00
|
|
|
*/
|
2018-09-18 07:49:40 +01:00
|
|
|
virtual u32 GetPSTATE() const = 0;
|
2014-04-05 06:23:28 +01:00
|
|
|
|
2014-05-12 03:14:13 +01:00
|
|
|
/**
|
2018-09-18 07:49:40 +01:00
|
|
|
* Set the current PSTATE register
|
|
|
|
* @param pstate Value to set PSTATE to
|
2014-05-12 03:14:13 +01:00
|
|
|
*/
|
2018-09-18 07:49:40 +01:00
|
|
|
virtual void SetPSTATE(u32 pstate) = 0;
|
2014-05-12 03:14:13 +01:00
|
|
|
|
2017-09-30 19:16:39 +01:00
|
|
|
virtual VAddr GetTlsAddress() const = 0;
|
|
|
|
|
|
|
|
virtual void SetTlsAddress(VAddr address) = 0;
|
|
|
|
|
2018-09-18 07:49:40 +01:00
|
|
|
/**
|
|
|
|
* Gets the value within the TPIDR_EL0 (read/write software thread ID) register.
|
|
|
|
*
|
|
|
|
* @return the value within the register.
|
|
|
|
*/
|
2018-07-21 01:57:45 +01:00
|
|
|
virtual u64 GetTPIDR_EL0() const = 0;
|
|
|
|
|
2018-09-18 07:49:40 +01:00
|
|
|
/**
|
|
|
|
* Sets a new value within the TPIDR_EL0 (read/write software thread ID) register.
|
|
|
|
*
|
|
|
|
* @param value The new value to place in the register.
|
|
|
|
*/
|
2018-07-21 01:57:45 +01:00
|
|
|
virtual void SetTPIDR_EL0(u64 value) = 0;
|
|
|
|
|
2014-05-20 23:50:16 +01:00
|
|
|
/**
|
|
|
|
* Saves the current CPU context
|
|
|
|
* @param ctx Thread context to save
|
|
|
|
*/
|
2016-12-22 05:08:09 +00:00
|
|
|
virtual void SaveContext(ThreadContext& ctx) = 0;
|
2014-05-20 23:50:16 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Loads a CPU context
|
|
|
|
* @param ctx Thread context to load
|
|
|
|
*/
|
2016-12-22 05:08:09 +00:00
|
|
|
virtual void LoadContext(const ThreadContext& ctx) = 0;
|
2014-05-20 23:50:16 +01:00
|
|
|
|
2018-09-18 07:49:40 +01:00
|
|
|
/// Clears the exclusive monitor's state.
|
2018-07-16 11:24:00 +01:00
|
|
|
virtual void ClearExclusiveState() = 0;
|
|
|
|
|
2014-06-02 02:40:10 +01:00
|
|
|
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
|
|
|
virtual void PrepareReschedule() = 0;
|
2018-12-03 09:13:48 +00:00
|
|
|
|
2018-12-19 03:10:51 +00:00
|
|
|
void LogBacktrace() {
|
|
|
|
VAddr fp = GetReg(29);
|
|
|
|
VAddr lr = GetReg(30);
|
|
|
|
VAddr sp = GetReg(13);
|
|
|
|
VAddr pc = GetPC();
|
|
|
|
LOG_ERROR(Core_ARM, "Backtrace, sp={:016X}, pc={:016X}", sp, pc);
|
|
|
|
for (;;) {
|
|
|
|
LOG_ERROR(Core_ARM, "{:016X}", lr);
|
|
|
|
if (!fp) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
lr = Memory::Read64(fp + 8) - 4;
|
|
|
|
fp = Memory::Read64(fp);
|
|
|
|
}
|
|
|
|
}
|
2014-04-05 03:26:06 +01:00
|
|
|
};
|
2018-08-25 02:43:32 +01:00
|
|
|
|
|
|
|
} // namespace Core
|