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156 lines
5.4 KiB
C++
156 lines
5.4 KiB
C++
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// This file implements the SSA rewriting algorithm proposed in
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//
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// Simple and Efficient Construction of Static Single Assignment Form.
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// Braun M., Buchwald S., Hack S., Lei<65>a R., Mallon C., Zwinkau A. (2013)
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// In: Jhala R., De Bosschere K. (eds)
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// Compiler Construction. CC 2013.
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// Lecture Notes in Computer Science, vol 7791.
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// Springer, Berlin, Heidelberg
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//
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// https://link.springer.com/chapter/10.1007/978-3-642-37051-9_6
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//
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#include <map>
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#include <boost/container/flat_map.hpp>
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/function.h"
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/frontend/ir/opcode.h"
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#include "shader_recompiler/frontend/ir/pred.h"
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#include "shader_recompiler/frontend/ir/reg.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Optimization {
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namespace {
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using ValueMap = boost::container::flat_map<IR::Block*, IR::Value, std::less<IR::Block*>>;
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struct DefTable {
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[[nodiscard]] ValueMap& operator[](IR::Reg variable) noexcept {
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return regs[IR::RegIndex(variable)];
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}
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[[nodiscard]] ValueMap& operator[](IR::Pred variable) noexcept {
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return preds[IR::PredIndex(variable)];
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}
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std::array<ValueMap, IR::NUM_USER_REGS> regs;
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std::array<ValueMap, IR::NUM_USER_PREDS> preds;
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};
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IR::Opcode UndefOpcode(IR::Reg) noexcept {
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return IR::Opcode::Undef32;
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}
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IR::Opcode UndefOpcode(IR::Pred) noexcept {
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return IR::Opcode::Undef1;
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}
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[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept {
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return inst.Opcode() == IR::Opcode::Phi;
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}
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class Pass {
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public:
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void WriteVariable(auto variable, IR::Block* block, const IR::Value& value) {
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current_def[variable].insert_or_assign(block, value);
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}
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IR::Value ReadVariable(auto variable, IR::Block* block) {
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auto& def{current_def[variable]};
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if (const auto it{def.find(block)}; it != def.end()) {
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return it->second;
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}
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return ReadVariableRecursive(variable, block);
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}
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private:
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IR::Value ReadVariableRecursive(auto variable, IR::Block* block) {
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IR::Value val;
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if (const std::span preds{block->ImmediatePredecessors()}; preds.size() == 1) {
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val = ReadVariable(variable, preds.front());
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} else {
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// Break potential cycles with operandless phi
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val = IR::Value{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
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WriteVariable(variable, block, val);
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val = AddPhiOperands(variable, val, block);
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}
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WriteVariable(variable, block, val);
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return val;
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}
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IR::Value AddPhiOperands(auto variable, const IR::Value& phi, IR::Block* block) {
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for (IR::Block* const pred : block->ImmediatePredecessors()) {
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phi.Inst()->AddPhiOperand(pred, ReadVariable(variable, pred));
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}
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return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
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}
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IR::Value TryRemoveTrivialPhi(const IR::Value& phi, IR::Block* block, IR::Opcode undef_opcode) {
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IR::Value same;
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for (const auto& pair : phi.Inst()->PhiOperands()) {
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const IR::Value& op{pair.second};
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if (op == same || op == phi) {
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// Unique value or self-reference
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continue;
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}
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if (!same.IsEmpty()) {
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// The phi merges at least two values: not trivial
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return phi;
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}
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same = op;
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}
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if (same.IsEmpty()) {
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// The phi is unreachable or in the start block
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const auto first_not_phi{std::ranges::find_if_not(block->Instructions(), IsPhi)};
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same = IR::Value{&*block->PrependNewInst(first_not_phi, undef_opcode)};
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}
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// Reroute all uses of phi to same and remove phi
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phi.Inst()->ReplaceUsesWith(same);
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// TODO: Try to recursively remove all phi users, which might have become trivial
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return same;
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}
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DefTable current_def;
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};
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} // Anonymous namespace
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void SsaRewritePass(IR::Function& function) {
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Pass pass;
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for (const auto& block : function.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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switch (inst.Opcode()) {
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case IR::Opcode::SetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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pass.WriteVariable(reg, block.get(), inst.Arg(1));
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}
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break;
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case IR::Opcode::SetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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pass.WriteVariable(pred, block.get(), inst.Arg(1));
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}
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break;
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case IR::Opcode::GetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block.get()));
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}
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break;
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case IR::Opcode::GetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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inst.ReplaceUsesWith(pass.ReadVariable(pred, block.get()));
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}
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break;
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default:
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break;
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}
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}
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}
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}
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} // namespace Shader::Optimization
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