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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #1812 from JayFoxRox/refactor-shader
Retrieve shader result from new OutputRegisters-type
This commit is contained in:
bunnei
commit
552018c50a
4 changed files with 81 additions and 64 deletions
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@ -149,7 +149,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation, static_cast<void*>(&immediate_input));
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Shader::OutputVertex output = g_state.vs.Run(shader_unit, immediate_input, regs.vs.num_input_attributes+1);
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g_state.vs.Run(shader_unit, immediate_input, regs.vs.num_input_attributes+1);
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Shader::OutputVertex output_vertex = shader_unit.output_registers.ToVertex(regs.vs);
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// Send to renderer
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using Pica::Shader::OutputVertex;
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@ -157,7 +158,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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VideoCore::g_renderer->Rasterizer()->AddTriangle(v0, v1, v2);
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};
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g_state.primitive_assembler.SubmitVertex(output, AddTriangle);
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g_state.primitive_assembler.SubmitVertex(output_vertex, AddTriangle);
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}
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}
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}
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@ -230,7 +231,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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// The size has been tuned for optimal balance between hit-rate and the cost of lookup
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const size_t VERTEX_CACHE_SIZE = 32;
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std::array<u16, VERTEX_CACHE_SIZE> vertex_cache_ids;
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std::array<Shader::OutputVertex, VERTEX_CACHE_SIZE> vertex_cache;
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std::array<Shader::OutputRegisters, VERTEX_CACHE_SIZE> vertex_cache;
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unsigned int vertex_cache_pos = 0;
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vertex_cache_ids.fill(-1);
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@ -248,7 +249,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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ASSERT(vertex != -1);
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bool vertex_cache_hit = false;
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Shader::OutputVertex output;
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Shader::OutputRegisters output_registers;
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if (is_indexed) {
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if (g_debug_context && Pica::g_debug_context->recorder) {
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@ -258,7 +259,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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for (unsigned int i = 0; i < VERTEX_CACHE_SIZE; ++i) {
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if (vertex == vertex_cache_ids[i]) {
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output = vertex_cache[i];
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output_registers = vertex_cache[i];
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vertex_cache_hit = true;
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break;
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}
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@ -273,15 +274,19 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation, (void*)&input);
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output = g_state.vs.Run(shader_unit, input, loader.GetNumTotalAttributes());
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g_state.vs.Run(shader_unit, input, loader.GetNumTotalAttributes());
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output_registers = shader_unit.output_registers;
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if (is_indexed) {
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vertex_cache[vertex_cache_pos] = output;
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vertex_cache[vertex_cache_pos] = output_registers;
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vertex_cache_ids[vertex_cache_pos] = vertex;
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vertex_cache_pos = (vertex_cache_pos + 1) % VERTEX_CACHE_SIZE;
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}
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}
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// Retreive vertex from register data
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Shader::OutputVertex output_vertex = output_registers.ToVertex(regs.vs);
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// Send to renderer
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using Pica::Shader::OutputVertex;
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auto AddTriangle = [](
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@ -289,7 +294,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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VideoCore::g_renderer->Rasterizer()->AddTriangle(v0, v1, v2);
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};
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primitive_assembler.SubmitVertex(output, AddTriangle);
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primitive_assembler.SubmitVertex(output_vertex, AddTriangle);
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}
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for (auto& range : memory_accesses.ranges) {
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@ -30,6 +30,58 @@ namespace Pica {
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namespace Shader {
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OutputVertex OutputRegisters::ToVertex(const Regs::ShaderConfig& config) {
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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unsigned index = 0;
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= g_state.regs.vs_output_total)
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break;
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if ((config.output_mask & (1 << i)) == 0)
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continue;
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const auto& output_register_map = g_state.regs.vs_output_attributes[index];
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (unsigned comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = value[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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index++;
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (unsigned i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(HW_GPU, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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"col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f), view(%.2f, %.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.quat.x.ToFloat32(), ret.quat.y.ToFloat32(), ret.quat.z.ToFloat32(), ret.quat.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32(),
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ret.view.x.ToFloat32(), ret.view.y.ToFloat32(), ret.view.z.ToFloat32());
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return ret;
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}
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#ifdef ARCHITECTURE_x86_64
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static std::unordered_map<u64, std::unique_ptr<JitShader>> shader_map;
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static const JitShader* jit_shader;
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@ -62,7 +114,7 @@ void ShaderSetup::Setup() {
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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OutputVertex ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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@ -89,55 +141,6 @@ OutputVertex ShaderSetup::Run(UnitState<false>& state, const InputVertex& input,
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RunInterpreter(setup, state, config.main_offset);
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#endif // ARCHITECTURE_x86_64
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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unsigned index = 0;
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= g_state.regs.vs_output_total)
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break;
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if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
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continue;
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const auto& output_register_map = g_state.regs.vs_output_attributes[index]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (unsigned comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.registers.output[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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index++;
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (unsigned i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(HW_GPU, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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"col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f), view(%.2f, %.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.quat.x.ToFloat32(), ret.quat.y.ToFloat32(), ret.quat.z.ToFloat32(), ret.quat.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32(),
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ret.view.x.ToFloat32(), ret.view.y.ToFloat32(), ret.view.z.ToFloat32());
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return ret;
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}
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DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const ShaderSetup& setup) {
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@ -84,6 +84,15 @@ struct OutputVertex {
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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struct OutputRegisters {
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OutputRegisters() = default;
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alignas(16) Math::Vec4<float24> value[16];
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OutputVertex ToVertex(const Regs::ShaderConfig& config);
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};
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static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
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// Helper structure used to keep track of data useful for inspection of shader emulation
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template<bool full_debugging>
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struct DebugData;
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@ -267,11 +276,12 @@ struct UnitState {
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// The registers are accessed by the shader JIT using SSE instructions, and are therefore
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// required to be 16-byte aligned.
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alignas(16) Math::Vec4<float24> input[16];
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alignas(16) Math::Vec4<float24> output[16];
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alignas(16) Math::Vec4<float24> temporary[16];
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} registers;
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static_assert(std::is_pod<Registers>::value, "Structure is not POD");
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OutputRegisters output_registers;
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bool conditional_code[2];
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// Two Address registers and one loop counter
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@ -297,7 +307,7 @@ struct UnitState {
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static size_t OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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return offsetof(UnitState, registers.output) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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return offsetof(UnitState, output_registers.value) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return offsetof(UnitState, registers.temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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@ -354,9 +364,8 @@ struct ShaderSetup {
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* @param state Shader unit state, must be setup per shader and per shader unit
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* @param input Input vertex into the shader
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* @param num_attributes The number of vertex shader attributes
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* @return The output vertex, after having been processed by the vertex shader
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*/
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OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attributes);
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void Run(UnitState<false>& state, const InputVertex& input, int num_attributes);
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/**
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* Produce debug information based on the given shader and input vertex
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@ -144,7 +144,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.common.dest.Value() < 0x10) ? &state.registers.output[instr.common.dest.Value().GetIndex()][0]
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float24* dest = (instr.common.dest.Value() < 0x10) ? &state.output_registers.value[instr.common.dest.Value().GetIndex()][0]
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: (instr.common.dest.Value() < 0x20) ? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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@ -483,7 +483,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
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src3[3] = src3[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.mad.dest.Value() < 0x10) ? &state.registers.output[instr.mad.dest.Value().GetIndex()][0]
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float24* dest = (instr.mad.dest.Value() < 0x10) ? &state.output_registers.value[instr.mad.dest.Value().GetIndex()][0]
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: (instr.mad.dest.Value() < 0x20) ? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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