mirrors/yuzu
2
1
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-07-04 23:31:19 +01:00
Code Issues Releases Activity

maxwell_3d: Add depth bounds registers

Browse source
This commit is contained in:
ReinUsesLisp 2019-11-06 01:39:41 -03:00
parent e976d0e924
commit 5770418fb3
No known key found for this signature in database
GPG key ID: 2DFC508897B39CFE
1 changed files with 14 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/video_core/engines/maxwell_3d.h
View file

@ -707,13 +707,15 @@ public:
u32 color_mask_common; u32 color_mask_common;
INSERT_UNION_PADDING_WORDS(0x6); INSERT_UNION_PADDING_WORDS(0x2);
u32 rt_separate_frag_data;
f32 depth_bounds[2]; f32 depth_bounds[2];
INSERT_UNION_PADDING_WORDS(0xA); INSERT_UNION_PADDING_WORDS(0x2);
u32 rt_separate_frag_data;
INSERT_UNION_PADDING_WORDS(0xC);
struct { struct {
u32 address_high; u32 address_high;
@ -1030,7 +1032,12 @@ public:
BitField<4, 1, u32> depth_clamp_far; BitField<4, 1, u32> depth_clamp_far;
} view_volume_clip_control; } view_volume_clip_control;
INSERT_UNION_PADDING_WORDS(0x21); INSERT_UNION_PADDING_WORDS(0x1F);
u32 depth_bounds_enable;
INSERT_UNION_PADDING_WORDS(1);
struct { struct {
u32 enable; u32 enable;
LogicOperation operation; LogicOperation operation;
@ -1439,7 +1446,7 @@ ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D6);
ASSERT_REG_POSITION(stencil_back_mask, 0x3D7); ASSERT_REG_POSITION(stencil_back_mask, 0x3D7);
ASSERT_REG_POSITION(color_mask_common, 0x3E4); ASSERT_REG_POSITION(color_mask_common, 0x3E4);
ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB); ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB);
ASSERT_REG_POSITION(depth_bounds, 0x3EC); ASSERT_REG_POSITION(depth_bounds, 0x3E7);
ASSERT_REG_POSITION(zeta, 0x3F8); ASSERT_REG_POSITION(zeta, 0x3F8);
ASSERT_REG_POSITION(clear_flags, 0x43E); ASSERT_REG_POSITION(clear_flags, 0x43E);
ASSERT_REG_POSITION(vertex_attrib_format, 0x458); ASSERT_REG_POSITION(vertex_attrib_format, 0x458);
@ -1495,6 +1502,7 @@ ASSERT_REG_POSITION(cull, 0x646);
ASSERT_REG_POSITION(pixel_center_integer, 0x649); ASSERT_REG_POSITION(pixel_center_integer, 0x649);
ASSERT_REG_POSITION(viewport_transform_enabled, 0x64B); ASSERT_REG_POSITION(viewport_transform_enabled, 0x64B);
ASSERT_REG_POSITION(view_volume_clip_control, 0x64F); ASSERT_REG_POSITION(view_volume_clip_control, 0x64F);
ASSERT_REG_POSITION(depth_bounds_enable, 0x66F);
ASSERT_REG_POSITION(logic_op, 0x671); ASSERT_REG_POSITION(logic_op, 0x671);
ASSERT_REG_POSITION(clear_buffers, 0x674); ASSERT_REG_POSITION(clear_buffers, 0x674);
ASSERT_REG_POSITION(color_mask, 0x680); ASSERT_REG_POSITION(color_mask, 0x680);