mirrors/yuzu
2
1
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-07-04 23:31:19 +01:00
Code Issues Releases Activity

Merge pull request #9010 from liamwhite/buttwise

Browse source 
macro_jit_x64: fix miscompilation of bit extraction operations
This commit is contained in:
bunnei 2022-10-04 15:52:39 -07:00 committed by GitHub
commit 92c0ad23eb
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 9 additions and 37 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

46
src/video_core/macro/macro_jit_x64.cpp
View file

@ -279,28 +279,13 @@ void MacroJITx64Impl::Compile_ExtractInsert(Macro::Opcode opcode) {
auto dst = Compile_GetRegister(opcode.src_a, RESULT); auto dst = Compile_GetRegister(opcode.src_a, RESULT);
auto src = Compile_GetRegister(opcode.src_b, eax); auto src = Compile_GetRegister(opcode.src_b, eax);
if (opcode.bf_src_bit != 0 && opcode.bf_src_bit != 31) {
shr(src, opcode.bf_src_bit);
} else if (opcode.bf_src_bit == 31) {
xor_(src, src);
}
// Don't bother masking the whole register since we're using a 32 bit register
if (opcode.bf_size != 31 && opcode.bf_size != 0) {
and_(src, opcode.GetBitfieldMask());
} else if (opcode.bf_size == 0) {
xor_(src, src);
}
if (opcode.bf_dst_bit != 31 && opcode.bf_dst_bit != 0) {
shl(src, opcode.bf_dst_bit);
} else if (opcode.bf_dst_bit == 31) {
xor_(src, src);
}
const u32 mask = ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit); const u32 mask = ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
if (mask != 0xffffffff) { and_(dst, mask);
and_(dst, mask); shr(src, opcode.bf_src_bit);
} and_(src, opcode.GetBitfieldMask());
shl(src, opcode.bf_dst_bit);
or_(dst, src); or_(dst, src);
Compile_ProcessResult(opcode.result_operation, opcode.dst); Compile_ProcessResult(opcode.result_operation, opcode.dst);
} }
@ -309,17 +294,9 @@ void MacroJITx64Impl::Compile_ExtractShiftLeftImmediate(Macro::Opcode opcode) {
const auto src = Compile_GetRegister(opcode.src_b, RESULT); const auto src = Compile_GetRegister(opcode.src_b, RESULT);
shr(src, dst.cvt8()); shr(src, dst.cvt8());
if (opcode.bf_size != 0 && opcode.bf_size != 31) { and_(src, opcode.GetBitfieldMask());
and_(src, opcode.GetBitfieldMask()); shl(src, opcode.bf_dst_bit);
} else if (opcode.bf_size == 0) {
xor_(src, src);
}
if (opcode.bf_dst_bit != 0 && opcode.bf_dst_bit != 31) {
shl(src, opcode.bf_dst_bit);
} else if (opcode.bf_dst_bit == 31) {
xor_(src, src);
}
Compile_ProcessResult(opcode.result_operation, opcode.dst); Compile_ProcessResult(opcode.result_operation, opcode.dst);
} }
@ -327,13 +304,8 @@ void MacroJITx64Impl::Compile_ExtractShiftLeftRegister(Macro::Opcode opcode) {
const auto dst = Compile_GetRegister(opcode.src_a, ecx); const auto dst = Compile_GetRegister(opcode.src_a, ecx);
const auto src = Compile_GetRegister(opcode.src_b, RESULT); const auto src = Compile_GetRegister(opcode.src_b, RESULT);
if (opcode.bf_src_bit != 0) { shr(src, opcode.bf_src_bit);
shr(src, opcode.bf_src_bit); and_(src, opcode.GetBitfieldMask());
}
if (opcode.bf_size != 31) {
and_(src, opcode.GetBitfieldMask());
}
shl(src, dst.cvt8()); shl(src, dst.cvt8());
Compile_ProcessResult(opcode.result_operation, opcode.dst); Compile_ProcessResult(opcode.result_operation, opcode.dst);